mirror of https://codeberg.org/topola/topola.git
tests: add signal integrity test board (4-layer) test data
This commit is contained in:
parent
e723c28f26
commit
c4ac090790
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mod common;
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#[test]
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fn test_prerouted_lm317_breakout() {
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let mut invoker = common::load_design_and_assert(
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"tests/multilayer/data/prerouted_lm317_breakout/unrouted_lm317_breakout.dsn",
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);
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}
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#[test]
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fn test_signal_integrity_test() {
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let mut invoker = common::load_design_and_assert(
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"tests/multilayer/data/signal_integrity_test/signal_integrity_test.dsn",
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);
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}
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@ -0,0 +1 @@
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0
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@ -0,0 +1,149 @@
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(pcb /home/mikolaj/proj/topola/tests/multilayer/signal_integrity_test/signal_integrity_test.dsn
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(parser
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(string_quote ")
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(space_in_quoted_tokens on)
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(host_cad "KiCad's Pcbnew")
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(host_version "8.0.2")
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)
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(resolution um 10)
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(unit um)
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(structure
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(layer F.Cu
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(type signal)
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(property
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(index 0)
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)
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)
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(layer In1.Cu
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(type signal)
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(property
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(index 1)
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)
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)
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(layer In2.Cu
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(type signal)
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(property
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(index 2)
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)
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)
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(layer B.Cu
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(type signal)
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(property
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(index 3)
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)
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)
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(boundary
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(path pcb 0 200660 -152400 104140 -152400 104140 -50800 200660 -50800
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200660 -152400)
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)
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(plane GND (polygon F.Cu 0 104140 -50800 200660 -50800 200660 -152400 104140 -152400
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104140 -50800))
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(plane GND (polygon B.Cu 0 104140 -50800 200660 -50800 200660 -152400 104140 -152400
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104140 -50800))
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(plane GND (polygon In1.Cu 0 104140 -50800 200660 -50800 200660 -152400 104140 -152400
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104140 -50800))
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(via "Via[0-3]_600:300_um" "Via[0-3]_2000:1000_um" "Via[0-2]_2000:1000_um")
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(rule
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(width 200)
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(clearance 200)
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(clearance 200 (type default_smd))
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(clearance 50 (type smd_smd))
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)
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)
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(placement
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(component Connector_Coaxial:SMA_Amphenol_132289_EdgeMount
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(place J2 197837.500000 -101600.000000 front 0.000000 (PN Conn_Coaxial))
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(place J1 106962.500000 -101600.000000 front 180.000000 (PN Conn_Coaxial))
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)
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)
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(library
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(image Connector_Coaxial:SMA_Amphenol_132289_EdgeMount
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(outline (path signal 120 -3710 250 -3710 -250))
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(outline (path signal 120 -3710 -250 -3210 0))
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(outline (path signal 120 -3210 0 -3710 250))
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(outline (path signal 50 -3040 -5580 -3040 5580))
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(outline (path signal 50 14470 5580 -3040 5580))
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(outline (path signal 50 14470 5580 14470 -5580))
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(outline (path signal 50 14470 -5580 -3040 -5580))
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(outline (path signal 50 -3040 -5580 -3040 5580))
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(outline (path signal 50 14470 5580 -3040 5580))
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(outline (path signal 50 14470 5580 14470 -5580))
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(outline (path signal 50 14470 -5580 -3040 -5580))
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(outline (path signal 100 -1910 5080 -1910 3810))
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(outline (path signal 100 -1910 5080 4445 5080))
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(outline (path signal 100 -1910 3810 2540 3810))
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(outline (path signal 100 -1910 -3810 -1910 -5080))
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(outline (path signal 100 -1910 -5080 4445 -5080))
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(outline (path signal 100 2540 3810 2540 -3810))
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(outline (path signal 100 2540 750 3540 0))
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(outline (path signal 100 2540 -3810 -1910 -3810))
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(outline (path signal 100 3540 0 2540 -750))
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(outline (path signal 100 4445 3810 4445 5080))
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(outline (path signal 100 4445 3810 13970 3810))
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(outline (path signal 100 4445 -5080 4445 -3810))
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(outline (path signal 100 13970 3810 13970 -3810))
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(outline (path signal 100 13970 -3810 4445 -3810))
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(pin Rect[T]Pad_1500x5080_um (rotate 90) 1 0 0)
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(pin Rect[T]Pad_1500x5080_um (rotate 90) 2 0 4250)
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(pin Rect[B]Pad_1500x5080_um (rotate 90) 2@1 0 4250)
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(pin Rect[T]Pad_1500x5080_um (rotate 90) 2@2 0 -4250)
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(pin Rect[B]Pad_1500x5080_um (rotate 90) 2@3 0 -4250)
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)
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(padstack Rect[B]Pad_1500x5080_um
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(shape (rect B.Cu -750 -2540 750 2540))
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(attach off)
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)
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(padstack Rect[T]Pad_1500x5080_um
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(shape (rect F.Cu -750 -2540 750 2540))
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(attach off)
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)
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(padstack "Via[0-3]_600:300_um"
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(shape (circle F.Cu 600))
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(shape (circle In1.Cu 600))
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(shape (circle In2.Cu 600))
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(shape (circle B.Cu 600))
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(attach off)
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)
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(padstack "Via[0-3]_2000:1000_um"
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(shape (circle F.Cu 2000))
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(shape (circle In1.Cu 2000))
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(shape (circle In2.Cu 2000))
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(shape (circle B.Cu 2000))
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(attach off)
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)
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(padstack "Via[0-2]_2000:1000_um"
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(shape (circle F.Cu 2000))
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(shape (circle In1.Cu 2000))
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(shape (circle In2.Cu 2000))
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(attach off)
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)
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)
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(network
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(net GND
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(pins J2-2 J2-2@1 J2-2@2 J2-2@3 J1-2 J1-2@1 J1-2@2 J1-2@3)
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)
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(net "Net-(J1-In)"
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(pins J2-1 J1-1)
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)
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(class kicad_default "" GND "Net-(J1-In)"
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(circuit
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(use_via Via[0-3]_600:300_um)
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)
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(rule
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(width 200)
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(clearance 200)
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)
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)
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)
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(wiring
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(wire (path In2.Cu 1000 110744 -101600 194056 -101600)(net "Net-(J1-In)")(type route))
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(wire (path F.Cu 1000 110744 -101600 106962 -101600)(net "Net-(J1-In)")(type route))
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(wire (path F.Cu 1000 197838 -101600 194310 -101600)(net "Net-(J1-In)")(type route))
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(via "Via[0-3]_2000:1000_um" 106680 -109220 (net GND)(type route))
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(via "Via[0-3]_2000:1000_um" 106680 -93980 (net GND)(type route))
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(via "Via[0-3]_2000:1000_um" 198120 -109220 (net GND)(type route))
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(via "Via[0-2]_2000:1000_um" 194056 -101600 (net "Net-(J1-In)")(type route))
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(via "Via[0-2]_2000:1000_um" 110744 -101600 (net "Net-(J1-In)")(type route))
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(via "Via[0-3]_2000:1000_um" 198120 -93980 (net GND)(type route))
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)
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)
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,83 @@
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{
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"board": {
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"active_layer": 0,
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"active_layer_preset": "All Layers",
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"auto_track_width": true,
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"hidden_netclasses": [],
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"hidden_nets": [],
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"high_contrast_mode": 0,
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"net_color_mode": 1,
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"opacity": {
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"images": 0.6,
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"pads": 1.0,
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"tracks": 1.0,
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"vias": 1.0,
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"zones": 0.6
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},
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"selection_filter": {
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"dimensions": true,
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"footprints": true,
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"graphics": true,
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"keepouts": true,
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"lockedItems": false,
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"otherItems": true,
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"pads": true,
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"text": true,
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"tracks": true,
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"vias": true,
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"zones": true
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},
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"visible_items": [
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0,
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1,
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2,
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36,
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39,
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40
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],
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"visible_layers": "fffffff_ffffffff",
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"zone_display_mode": 0
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},
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"git": {
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"repo_password": "",
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"repo_type": "",
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"repo_username": "",
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"ssh_key": ""
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},
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"meta": {
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"filename": "signal_integrity_test.kicad_prl",
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"version": 3
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},
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"project": {
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"files": []
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}
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}
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|
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@ -0,0 +1,391 @@
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{
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"board": {
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"3dviewports": [],
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"design_settings": {
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"defaults": {},
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"diff_pair_dimensions": [],
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"drc_exclusions": [],
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"rules": {},
|
||||
"track_widths": [],
|
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"via_dimensions": []
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||||
},
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"ipc2581": {
|
||||
"dist": "",
|
||||
"distpn": "",
|
||||
"internal_id": "",
|
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"mfg": "",
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"mpn": ""
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},
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"layer_presets": [],
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"viewports": []
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},
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"boards": [],
|
||||
"cvpcb": {
|
||||
"equivalence_files": []
|
||||
},
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"erc": {
|
||||
"erc_exclusions": [],
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"meta": {
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"version": 0
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},
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"pin_map": [
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[
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0,
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0,
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0,
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0,
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0,
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1,
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],
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[
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],
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[
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0,
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0,
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0,
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1,
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0,
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1,
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],
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[
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1,
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],
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[
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],
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[
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2,
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2,
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2,
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2,
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2,
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2,
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2,
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2,
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2,
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2,
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2,
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2
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]
|
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],
|
||||
"rule_severities": {
|
||||
"bus_definition_conflict": "error",
|
||||
"bus_entry_needed": "error",
|
||||
"bus_to_bus_conflict": "error",
|
||||
"bus_to_net_conflict": "error",
|
||||
"conflicting_netclasses": "error",
|
||||
"different_unit_footprint": "error",
|
||||
"different_unit_net": "error",
|
||||
"duplicate_reference": "error",
|
||||
"duplicate_sheet_names": "error",
|
||||
"endpoint_off_grid": "warning",
|
||||
"extra_units": "error",
|
||||
"global_label_dangling": "warning",
|
||||
"hier_label_mismatch": "error",
|
||||
"label_dangling": "error",
|
||||
"lib_symbol_issues": "warning",
|
||||
"missing_bidi_pin": "warning",
|
||||
"missing_input_pin": "warning",
|
||||
"missing_power_pin": "error",
|
||||
"missing_unit": "warning",
|
||||
"multiple_net_names": "warning",
|
||||
"net_not_bus_member": "warning",
|
||||
"no_connect_connected": "warning",
|
||||
"no_connect_dangling": "warning",
|
||||
"pin_not_connected": "error",
|
||||
"pin_not_driven": "error",
|
||||
"pin_to_pin": "warning",
|
||||
"power_pin_not_driven": "error",
|
||||
"similar_labels": "warning",
|
||||
"simulation_model_issue": "ignore",
|
||||
"unannotated": "error",
|
||||
"unit_value_mismatch": "error",
|
||||
"unresolved_variable": "error",
|
||||
"wire_dangling": "error"
|
||||
}
|
||||
},
|
||||
"libraries": {
|
||||
"pinned_footprint_libs": [],
|
||||
"pinned_symbol_libs": []
|
||||
},
|
||||
"meta": {
|
||||
"filename": "signal_integrity_test.kicad_pro",
|
||||
"version": 1
|
||||
},
|
||||
"net_settings": {
|
||||
"classes": [
|
||||
{
|
||||
"bus_width": 12,
|
||||
"clearance": 0.2,
|
||||
"diff_pair_gap": 0.25,
|
||||
"diff_pair_via_gap": 0.25,
|
||||
"diff_pair_width": 0.2,
|
||||
"line_style": 0,
|
||||
"microvia_diameter": 0.3,
|
||||
"microvia_drill": 0.1,
|
||||
"name": "Default",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 0.2,
|
||||
"via_diameter": 0.6,
|
||||
"via_drill": 0.3,
|
||||
"wire_width": 6
|
||||
}
|
||||
],
|
||||
"meta": {
|
||||
"version": 3
|
||||
},
|
||||
"net_colors": null,
|
||||
"netclass_assignments": null,
|
||||
"netclass_patterns": []
|
||||
},
|
||||
"pcbnew": {
|
||||
"last_paths": {
|
||||
"gencad": "",
|
||||
"idf": "",
|
||||
"netlist": "",
|
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(at 177.8 101.6 0)
|
||||
(effects
|
||||
(font
|
||||
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|
||||
)
|
||||
(hide yes)
|
||||
)
|
||||
)
|
||||
(property "Datasheet" " ~"
|
||||
(at 177.8 101.6 0)
|
||||
(effects
|
||||
(font
|
||||
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|
||||
)
|
||||
(hide yes)
|
||||
)
|
||||
)
|
||||
(property "Description" "coaxial connector (BNC, SMA, SMB, SMC, Cinch/RCA, LEMO, ...)"
|
||||
(at 177.8 101.6 0)
|
||||
(effects
|
||||
(font
|
||||
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|
||||
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|
||||
(hide yes)
|
||||
)
|
||||
)
|
||||
(pin "2"
|
||||
(uuid "27edd9ee-fcb1-458b-b797-49d9083d6c9d")
|
||||
)
|
||||
(pin "1"
|
||||
(uuid "a93b124e-47bc-48d2-82dd-cc12cf95c57d")
|
||||
)
|
||||
(instances
|
||||
(project "signal_integrity_test"
|
||||
(path "/b2bb4ae5-4d76-4744-9456-126b3d3290e1"
|
||||
(reference "J2")
|
||||
(unit 1)
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
(symbol
|
||||
(lib_id "power:GND")
|
||||
(at 127 106.68 0)
|
||||
(unit 1)
|
||||
(exclude_from_sim no)
|
||||
(in_bom yes)
|
||||
(on_board yes)
|
||||
(dnp no)
|
||||
(fields_autoplaced yes)
|
||||
(uuid "f6c2f185-e5bd-4276-85c4-b00849844f55")
|
||||
(property "Reference" "#PWR02"
|
||||
(at 127 113.03 0)
|
||||
(effects
|
||||
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|
||||
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|
||||
)
|
||||
(hide yes)
|
||||
)
|
||||
)
|
||||
(property "Value" "GND"
|
||||
(at 127 111.76 0)
|
||||
(effects
|
||||
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|
||||
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|
||||
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|
||||
)
|
||||
)
|
||||
(property "Footprint" ""
|
||||
(at 127 106.68 0)
|
||||
(effects
|
||||
(font
|
||||
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|
||||
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|
||||
(hide yes)
|
||||
)
|
||||
)
|
||||
(property "Datasheet" ""
|
||||
(at 127 106.68 0)
|
||||
(effects
|
||||
(font
|
||||
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|
||||
)
|
||||
(hide yes)
|
||||
)
|
||||
)
|
||||
(property "Description" "Power symbol creates a global label with name \"GND\" , ground"
|
||||
(at 127 106.68 0)
|
||||
(effects
|
||||
(font
|
||||
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|
||||
)
|
||||
(hide yes)
|
||||
)
|
||||
)
|
||||
(pin "1"
|
||||
(uuid "808c0cb9-415c-41a8-aac6-d78e8ce64938")
|
||||
)
|
||||
(instances
|
||||
(project "signal_integrity_test"
|
||||
(path "/b2bb4ae5-4d76-4744-9456-126b3d3290e1"
|
||||
(reference "#PWR02")
|
||||
(unit 1)
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
(sheet_instances
|
||||
(path "/"
|
||||
(page "1")
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1 @@
|
|||
{"hostname":"luckmann","username":"mikolaj"}
|
||||
Loading…
Reference in New Issue