From c4ac0907908cbbd493372b98e95d2aeeb21c8f97 Mon Sep 17 00:00:00 2001 From: Mikolaj Wielgus Date: Fri, 14 Jun 2024 23:21:33 +0200 Subject: [PATCH] tests: add signal integrity test board (4-layer) test data --- tests/multilayer.rs | 15 + .../prerouted_lm317_breakout/fp-info-cache | 0 .../prerouted_lm317_breakout.dsn | 0 .../prerouted_lm317_breakout.kicad_pcb | 0 .../prerouted_lm317_breakout.kicad_prl | 0 .../prerouted_lm317_breakout.kicad_pro | 0 .../prerouted_lm317_breakout.kicad_sch | 0 .../unrouted_lm317_breakout.dsn | 0 .../data/signal_integrity_test/fp-info-cache | 1 + .../signal_integrity_test.dsn | 149 ++ .../signal_integrity_test.kicad_pcb | 1259 +++++++++++++++++ .../signal_integrity_test.kicad_prl | 83 ++ .../signal_integrity_test.kicad_pro | 391 +++++ .../signal_integrity_test.kicad_sch | 555 ++++++++ .../~signal_integrity_test.kicad_pcb.lck | 1 + 15 files changed, 2454 insertions(+) create mode 100644 tests/multilayer.rs rename tests/multilayer/{ => data}/prerouted_lm317_breakout/fp-info-cache (100%) rename tests/multilayer/{ => data}/prerouted_lm317_breakout/prerouted_lm317_breakout.dsn (100%) rename tests/multilayer/{ => data}/prerouted_lm317_breakout/prerouted_lm317_breakout.kicad_pcb (100%) rename tests/multilayer/{ => data}/prerouted_lm317_breakout/prerouted_lm317_breakout.kicad_prl (100%) rename tests/multilayer/{ => data}/prerouted_lm317_breakout/prerouted_lm317_breakout.kicad_pro (100%) rename tests/multilayer/{ => data}/prerouted_lm317_breakout/prerouted_lm317_breakout.kicad_sch (100%) rename tests/multilayer/{ => data}/prerouted_lm317_breakout/unrouted_lm317_breakout.dsn (100%) create mode 100644 tests/multilayer/data/signal_integrity_test/fp-info-cache create mode 100644 tests/multilayer/data/signal_integrity_test/signal_integrity_test.dsn create mode 100644 tests/multilayer/data/signal_integrity_test/signal_integrity_test.kicad_pcb create mode 100644 tests/multilayer/data/signal_integrity_test/signal_integrity_test.kicad_prl create mode 100644 tests/multilayer/data/signal_integrity_test/signal_integrity_test.kicad_pro create mode 100644 tests/multilayer/data/signal_integrity_test/signal_integrity_test.kicad_sch create mode 100644 tests/multilayer/data/signal_integrity_test/~signal_integrity_test.kicad_pcb.lck diff --git a/tests/multilayer.rs b/tests/multilayer.rs new file mode 100644 index 0000000..26ce1be --- /dev/null +++ b/tests/multilayer.rs @@ -0,0 +1,15 @@ +mod common; + +#[test] +fn test_prerouted_lm317_breakout() { + let mut invoker = common::load_design_and_assert( + "tests/multilayer/data/prerouted_lm317_breakout/unrouted_lm317_breakout.dsn", + ); +} + +#[test] +fn test_signal_integrity_test() { + let mut invoker = common::load_design_and_assert( + "tests/multilayer/data/signal_integrity_test/signal_integrity_test.dsn", + ); +} diff --git a/tests/multilayer/prerouted_lm317_breakout/fp-info-cache b/tests/multilayer/data/prerouted_lm317_breakout/fp-info-cache similarity index 100% rename from tests/multilayer/prerouted_lm317_breakout/fp-info-cache rename to tests/multilayer/data/prerouted_lm317_breakout/fp-info-cache diff --git a/tests/multilayer/prerouted_lm317_breakout/prerouted_lm317_breakout.dsn b/tests/multilayer/data/prerouted_lm317_breakout/prerouted_lm317_breakout.dsn similarity index 100% rename from tests/multilayer/prerouted_lm317_breakout/prerouted_lm317_breakout.dsn rename to tests/multilayer/data/prerouted_lm317_breakout/prerouted_lm317_breakout.dsn diff --git a/tests/multilayer/prerouted_lm317_breakout/prerouted_lm317_breakout.kicad_pcb b/tests/multilayer/data/prerouted_lm317_breakout/prerouted_lm317_breakout.kicad_pcb similarity index 100% rename from tests/multilayer/prerouted_lm317_breakout/prerouted_lm317_breakout.kicad_pcb rename to tests/multilayer/data/prerouted_lm317_breakout/prerouted_lm317_breakout.kicad_pcb diff --git a/tests/multilayer/prerouted_lm317_breakout/prerouted_lm317_breakout.kicad_prl b/tests/multilayer/data/prerouted_lm317_breakout/prerouted_lm317_breakout.kicad_prl similarity index 100% rename from tests/multilayer/prerouted_lm317_breakout/prerouted_lm317_breakout.kicad_prl rename to tests/multilayer/data/prerouted_lm317_breakout/prerouted_lm317_breakout.kicad_prl diff --git a/tests/multilayer/prerouted_lm317_breakout/prerouted_lm317_breakout.kicad_pro b/tests/multilayer/data/prerouted_lm317_breakout/prerouted_lm317_breakout.kicad_pro similarity index 100% rename from tests/multilayer/prerouted_lm317_breakout/prerouted_lm317_breakout.kicad_pro rename to tests/multilayer/data/prerouted_lm317_breakout/prerouted_lm317_breakout.kicad_pro diff --git a/tests/multilayer/prerouted_lm317_breakout/prerouted_lm317_breakout.kicad_sch b/tests/multilayer/data/prerouted_lm317_breakout/prerouted_lm317_breakout.kicad_sch similarity index 100% rename from tests/multilayer/prerouted_lm317_breakout/prerouted_lm317_breakout.kicad_sch rename to tests/multilayer/data/prerouted_lm317_breakout/prerouted_lm317_breakout.kicad_sch diff --git a/tests/multilayer/prerouted_lm317_breakout/unrouted_lm317_breakout.dsn b/tests/multilayer/data/prerouted_lm317_breakout/unrouted_lm317_breakout.dsn similarity index 100% rename from tests/multilayer/prerouted_lm317_breakout/unrouted_lm317_breakout.dsn rename to tests/multilayer/data/prerouted_lm317_breakout/unrouted_lm317_breakout.dsn diff --git a/tests/multilayer/data/signal_integrity_test/fp-info-cache b/tests/multilayer/data/signal_integrity_test/fp-info-cache new file mode 100644 index 0000000..573541a --- /dev/null +++ b/tests/multilayer/data/signal_integrity_test/fp-info-cache @@ -0,0 +1 @@ +0 diff --git a/tests/multilayer/data/signal_integrity_test/signal_integrity_test.dsn b/tests/multilayer/data/signal_integrity_test/signal_integrity_test.dsn new file mode 100644 index 0000000..3a9a8d4 --- /dev/null +++ b/tests/multilayer/data/signal_integrity_test/signal_integrity_test.dsn @@ -0,0 +1,149 @@ +(pcb /home/mikolaj/proj/topola/tests/multilayer/signal_integrity_test/signal_integrity_test.dsn + (parser + (string_quote ") + (space_in_quoted_tokens on) + (host_cad "KiCad's Pcbnew") + (host_version "8.0.2") + ) + (resolution um 10) + (unit um) + (structure + (layer F.Cu + (type signal) + (property + (index 0) + ) + ) + (layer In1.Cu + (type signal) + (property + (index 1) + ) + ) + (layer In2.Cu + (type signal) + (property + (index 2) + ) + ) + (layer B.Cu + (type signal) + (property + (index 3) + ) + ) + (boundary + (path pcb 0 200660 -152400 104140 -152400 104140 -50800 200660 -50800 + 200660 -152400) + ) + (plane GND (polygon F.Cu 0 104140 -50800 200660 -50800 200660 -152400 104140 -152400 + 104140 -50800)) + (plane GND (polygon B.Cu 0 104140 -50800 200660 -50800 200660 -152400 104140 -152400 + 104140 -50800)) + (plane GND (polygon In1.Cu 0 104140 -50800 200660 -50800 200660 -152400 104140 -152400 + 104140 -50800)) + (via "Via[0-3]_600:300_um" "Via[0-3]_2000:1000_um" "Via[0-2]_2000:1000_um") + (rule + (width 200) + (clearance 200) + (clearance 200 (type default_smd)) + (clearance 50 (type smd_smd)) + ) + ) + (placement + (component Connector_Coaxial:SMA_Amphenol_132289_EdgeMount + (place J2 197837.500000 -101600.000000 front 0.000000 (PN Conn_Coaxial)) + (place J1 106962.500000 -101600.000000 front 180.000000 (PN Conn_Coaxial)) + ) + ) + (library + (image Connector_Coaxial:SMA_Amphenol_132289_EdgeMount + (outline (path signal 120 -3710 250 -3710 -250)) + (outline (path signal 120 -3710 -250 -3210 0)) + (outline (path signal 120 -3210 0 -3710 250)) + (outline (path signal 50 -3040 -5580 -3040 5580)) + (outline (path signal 50 14470 5580 -3040 5580)) + (outline (path signal 50 14470 5580 14470 -5580)) + (outline (path signal 50 14470 -5580 -3040 -5580)) + (outline (path signal 50 -3040 -5580 -3040 5580)) + (outline (path signal 50 14470 5580 -3040 5580)) + (outline (path signal 50 14470 5580 14470 -5580)) + (outline (path signal 50 14470 -5580 -3040 -5580)) + (outline (path signal 100 -1910 5080 -1910 3810)) + (outline (path signal 100 -1910 5080 4445 5080)) + (outline (path signal 100 -1910 3810 2540 3810)) + (outline (path signal 100 -1910 -3810 -1910 -5080)) + (outline (path signal 100 -1910 -5080 4445 -5080)) + (outline (path signal 100 2540 3810 2540 -3810)) + (outline (path signal 100 2540 750 3540 0)) + (outline (path signal 100 2540 -3810 -1910 -3810)) + (outline (path signal 100 3540 0 2540 -750)) + (outline (path signal 100 4445 3810 4445 5080)) + (outline (path signal 100 4445 3810 13970 3810)) + (outline (path signal 100 4445 -5080 4445 -3810)) + (outline (path signal 100 13970 3810 13970 -3810)) + (outline (path signal 100 13970 -3810 4445 -3810)) + (pin Rect[T]Pad_1500x5080_um (rotate 90) 1 0 0) + (pin Rect[T]Pad_1500x5080_um (rotate 90) 2 0 4250) + (pin Rect[B]Pad_1500x5080_um (rotate 90) 2@1 0 4250) + (pin Rect[T]Pad_1500x5080_um (rotate 90) 2@2 0 -4250) + (pin Rect[B]Pad_1500x5080_um (rotate 90) 2@3 0 -4250) + ) + (padstack Rect[B]Pad_1500x5080_um + (shape (rect B.Cu -750 -2540 750 2540)) + (attach off) + ) + (padstack Rect[T]Pad_1500x5080_um + (shape (rect F.Cu -750 -2540 750 2540)) + (attach off) + ) + (padstack "Via[0-3]_600:300_um" + (shape (circle F.Cu 600)) + (shape (circle In1.Cu 600)) + (shape (circle In2.Cu 600)) + (shape (circle B.Cu 600)) + (attach off) + ) + (padstack "Via[0-3]_2000:1000_um" + (shape (circle F.Cu 2000)) + (shape (circle In1.Cu 2000)) + (shape (circle In2.Cu 2000)) + (shape (circle B.Cu 2000)) + (attach off) + ) + (padstack "Via[0-2]_2000:1000_um" + (shape (circle F.Cu 2000)) + (shape (circle In1.Cu 2000)) + (shape (circle In2.Cu 2000)) + (attach off) + ) + ) + (network + (net GND + (pins J2-2 J2-2@1 J2-2@2 J2-2@3 J1-2 J1-2@1 J1-2@2 J1-2@3) + ) + (net "Net-(J1-In)" + (pins J2-1 J1-1) + ) + (class kicad_default "" GND "Net-(J1-In)" + (circuit + (use_via Via[0-3]_600:300_um) + ) + (rule + (width 200) + (clearance 200) + ) + ) + ) + (wiring + (wire (path In2.Cu 1000 110744 -101600 194056 -101600)(net "Net-(J1-In)")(type route)) + (wire (path F.Cu 1000 110744 -101600 106962 -101600)(net "Net-(J1-In)")(type route)) + (wire (path F.Cu 1000 197838 -101600 194310 -101600)(net "Net-(J1-In)")(type route)) + (via "Via[0-3]_2000:1000_um" 106680 -109220 (net GND)(type route)) + (via "Via[0-3]_2000:1000_um" 106680 -93980 (net GND)(type route)) + (via "Via[0-3]_2000:1000_um" 198120 -109220 (net GND)(type route)) + (via "Via[0-2]_2000:1000_um" 194056 -101600 (net "Net-(J1-In)")(type route)) + (via "Via[0-2]_2000:1000_um" 110744 -101600 (net "Net-(J1-In)")(type route)) + (via "Via[0-3]_2000:1000_um" 198120 -93980 (net GND)(type route)) + ) +) diff --git a/tests/multilayer/data/signal_integrity_test/signal_integrity_test.kicad_pcb b/tests/multilayer/data/signal_integrity_test/signal_integrity_test.kicad_pcb new file mode 100644 index 0000000..6194de5 --- /dev/null +++ b/tests/multilayer/data/signal_integrity_test/signal_integrity_test.kicad_pcb @@ -0,0 +1,1259 @@ +(kicad_pcb + (version 20240108) + (generator "pcbnew") + (generator_version "8.0") + (general + (thickness 1.6) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (1 "In1.Cu" signal) + (2 "In2.Cu" signal) + (31 "B.Cu" signal) + (32 "B.Adhes" user "B.Adhesive") + (33 "F.Adhes" user "F.Adhesive") + (34 "B.Paste" user) + (35 "F.Paste" user) + (36 "B.SilkS" user "B.Silkscreen") + (37 "F.SilkS" user "F.Silkscreen") + (38 "B.Mask" user) + (39 "F.Mask" user) + (40 "Dwgs.User" user "User.Drawings") + (41 "Cmts.User" user "User.Comments") + (42 "Eco1.User" user "User.Eco1") + (43 "Eco2.User" user "User.Eco2") + (44 "Edge.Cuts" user) + (45 "Margin" user) + (46 "B.CrtYd" user "B.Courtyard") + (47 "F.CrtYd" user "F.Courtyard") + (48 "B.Fab" user) + (49 "F.Fab" user) + (50 "User.1" user) + (51 "User.2" user) + (52 "User.3" user) + (53 "User.4" user) + (54 "User.5" user) + (55 "User.6" user) + (56 "User.7" user) + (57 "User.8" user) + (58 "User.9" user) + ) + (setup + (stackup + (layer "F.SilkS" + (type "Top Silk Screen") + ) + (layer "F.Paste" + (type "Top Solder Paste") + ) + (layer "F.Mask" + (type "Top Solder Mask") + (thickness 0.01) + ) + (layer "F.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "dielectric 1" + (type "prepreg") + (thickness 0.1) + (material "FR4") + (epsilon_r 4.5) + (loss_tangent 0.02) + ) + (layer "In1.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "dielectric 2" + (type "core") + (thickness 1.24) + (material "FR4") + (epsilon_r 4.5) + (loss_tangent 0.02) + ) + (layer "In2.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "dielectric 3" + (type "prepreg") + (thickness 0.1) + (material "FR4") + (epsilon_r 4.5) + (loss_tangent 0.02) + ) + (layer "B.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "B.Mask" + (type "Bottom Solder Mask") + (thickness 0.01) + ) + (layer "B.Paste" + (type "Bottom Solder Paste") + ) + (layer "B.SilkS" + (type "Bottom Silk Screen") + ) + (copper_finish "None") + (dielectric_constraints no) + ) + (pad_to_mask_clearance 0) + (allow_soldermask_bridges_in_footprints no) + (pcbplotparams + (layerselection 0x00010fc_ffffffff) + (plot_on_all_layers_selection 0x0000000_00000000) + (disableapertmacros no) + (usegerberextensions no) + (usegerberattributes yes) + (usegerberadvancedattributes yes) + (creategerberjobfile yes) + (dashed_line_dash_ratio 12.000000) + (dashed_line_gap_ratio 3.000000) + (svgprecision 4) + (plotframeref no) + (viasonmask no) + (mode 1) + (useauxorigin no) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15.000000) + (pdf_front_fp_property_popups yes) + (pdf_back_fp_property_popups yes) + (dxfpolygonmode yes) + (dxfimperialunits yes) + (dxfusepcbnewfont yes) + (psnegative no) + (psa4output no) + (plotreference yes) + (plotvalue yes) + (plotfptext yes) + (plotinvisibletext no) + (sketchpadsonfab no) + (subtractmaskfromsilk no) + (outputformat 1) + (mirror no) + (drillshape 1) + (scaleselection 1) + (outputdirectory "") + ) + ) + (net 0 "") + (net 1 "GND") + (net 2 "Net-(J1-In)") + (footprint "Connector_Coaxial:SMA_Amphenol_132289_EdgeMount" + (layer "F.Cu") + (uuid "21d52dc3-6a4b-480a-a2ec-25196e53bd75") + (at 106.9625 101.6 180) + (descr "http://www.amphenolrf.com/132289.html") + (tags "SMA") + (property "Reference" "J1" + (at -3.96 -3 270) + (layer "F.SilkS") + (uuid "bbd829af-9500-4988-853c-3ef33f0bba1f") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Value" "Conn_Coaxial" + (at 5 6 180) + (layer "F.Fab") + (uuid "09a5c102-fe4e-4d2a-9014-abbe65850552") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Footprint" "Connector_Coaxial:SMA_Amphenol_132289_EdgeMount" + (at 0 0 180) + (unlocked yes) + (layer "F.Fab") + (hide yes) + (uuid "d6a4e83d-d38f-4e3f-8e75-93961d8c28cb") + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Datasheet" " ~" + (at 0 0 180) + (unlocked yes) + (layer "F.Fab") + (hide yes) + (uuid "969f418e-eb6d-45f0-a431-3320e19ac89a") + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Description" "coaxial connector (BNC, SMA, SMB, SMC, Cinch/RCA, LEMO, ...)" + (at 0 0 180) + (unlocked yes) + (layer "F.Fab") + (hide yes) + (uuid "6f3af189-d9a9-4dfb-8d58-6d026d5ea385") + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property ki_fp_filters "*BNC* *SMA* *SMB* *SMC* *Cinch* *LEMO* *UMRF* *MCX* *U.FL*") + (path "/aca9e571-283a-4ba3-9d0d-a0ba4c2dc9f4") + (sheetname "Root") + (sheetfile "signal_integrity_test.kicad_sch") + (attr smd) + (fp_line + (start -3.21 0) + (end -3.71 -0.25) + (stroke + (width 0.12) + (type solid) + ) + (layer "F.SilkS") + (uuid "d36dc6f2-001e-48a4-a772-a4c2972f5baa") + ) + (fp_line + (start -3.71 0.25) + (end -3.21 0) + (stroke + (width 0.12) + (type solid) + ) + (layer "F.SilkS") + (uuid "4da4ba7e-5049-4119-be8b-bdaaaad3aaf0") + ) + (fp_line + (start -3.71 -0.25) + (end -3.71 0.25) + (stroke + (width 0.12) + (type solid) + ) + (layer "F.SilkS") + (uuid "9a712596-66df-445a-9d4e-a6334cdc472f") + ) + (fp_line + (start 14.47 5.58) + (end -3.04 5.58) + (stroke + (width 0.05) + (type solid) + ) + (layer "B.CrtYd") + (uuid "b59735ff-605d-4c5f-8029-a1f5a63ec85d") + ) + (fp_line + (start 14.47 -5.58) + (end 14.47 5.58) + (stroke + (width 0.05) + (type solid) + ) + (layer "B.CrtYd") + (uuid "13fa046c-2b82-4737-896d-ac6a23213528") + ) + (fp_line + (start 14.47 -5.58) + (end -3.04 -5.58) + (stroke + (width 0.05) + (type solid) + ) + (layer "B.CrtYd") + (uuid "5f9ac6e9-f366-4354-87cf-e0ac618af17c") + ) + (fp_line + (start -3.04 5.58) + (end -3.04 -5.58) + (stroke + (width 0.05) + (type solid) + ) + (layer "B.CrtYd") + (uuid "03048688-1858-4c6c-bcec-d738c63b88df") + ) + (fp_line + (start 14.47 5.58) + (end -3.04 5.58) + (stroke + (width 0.05) + (type solid) + ) + (layer "F.CrtYd") + (uuid "19d54e63-08d1-42da-8d09-d8c52aa6d7cf") + ) + (fp_line + (start 14.47 -5.58) + (end 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