270 lines
8.5 KiB
Rust
270 lines
8.5 KiB
Rust
/*
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* MIT License
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*
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* Copyright (c) 2018-2019 Andre Richter <andre.o.richter@gmail.com>
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* Copyright (c) 2019 Berkus Decker <berkus+github@metta.systems>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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use super::mailbox;
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use crate::arch::{loop_delay, loop_until};
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use crate::devices::ConsoleOps;
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use crate::platform::{gpio, rpi3::BcmHost};
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use core::{convert::TryFrom, ops};
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use register::{mmio::*, register_bitfields};
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// PL011 UART registers.
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//
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// Descriptions taken from
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// https://github.com/raspberrypi/documentation/files/1888662/BCM2837-ARM-Peripherals.-.Revised.-.V2-1.pdf
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register_bitfields! {
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u32,
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/// Flag Register
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FR [
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/// Transmit FIFO full. The meaning of this bit depends on the
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/// state of the FEN bit in the UARTLCR_ LCRH Register. If the
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/// FIFO is disabled, this bit is set when the transmit
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/// holding register is full. If the FIFO is enabled, the TXFF
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/// bit is set when the transmit FIFO is full.
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TXFF OFFSET(5) NUMBITS(1) [],
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/// Receive FIFO empty. The meaning of this bit depends on the
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/// state of the FEN bit in the UARTLCR_H Register. If the
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/// FIFO is disabled, this bit is set when the receive holding
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/// register is empty. If the FIFO is enabled, the RXFE bit is
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/// set when the receive FIFO is empty.
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RXFE OFFSET(4) NUMBITS(1) []
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],
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/// Integer Baud rate divisor
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IBRD [
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/// Integer Baud rate divisor
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IBRD OFFSET(0) NUMBITS(16) []
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],
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/// Fractional Baud rate divisor
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FBRD [
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/// Fractional Baud rate divisor
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FBRD OFFSET(0) NUMBITS(6) []
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],
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/// Line Control register
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LCRH [
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/// Word length. These bits indicate the number of data bits
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/// transmitted or received in a frame.
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WLEN OFFSET(5) NUMBITS(2) [
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FiveBit = 0b00,
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SixBit = 0b01,
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SevenBit = 0b10,
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EightBit = 0b11
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]
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],
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/// Control Register
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CR [
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/// Receive enable. If this bit is set to 1, the receive
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/// section of the UART is enabled. Data reception occurs for
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/// UART signals. When the UART is disabled in the middle of
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/// reception, it completes the current character before
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/// stopping.
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RXE OFFSET(9) NUMBITS(1) [
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Disabled = 0,
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Enabled = 1
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],
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/// Transmit enable. If this bit is set to 1, the transmit
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/// section of the UART is enabled. Data transmission occurs
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/// for UART signals. When the UART is disabled in the middle
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/// of transmission, it completes the current character before
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/// stopping.
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TXE OFFSET(8) NUMBITS(1) [
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Disabled = 0,
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Enabled = 1
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],
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/// UART enable
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UARTEN OFFSET(0) NUMBITS(1) [
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/// If the UART is disabled in the middle of transmission
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/// or reception, it completes the current character
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/// before stopping.
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Disabled = 0,
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Enabled = 1
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]
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],
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/// Interupt Clear Register
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ICR [
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/// Meta field for all pending interrupts
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ALL OFFSET(0) NUMBITS(11) []
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]
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}
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#[allow(non_snake_case)]
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#[repr(C)]
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pub struct RegisterBlock {
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DR: ReadWrite<u32>, // 0x00
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__reserved_0: [u32; 5], // 0x04 (UART0_RSRECR=0x04)
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FR: ReadOnly<u32, FR::Register>, // 0x18
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__reserved_1: [u32; 1], // 0x1c
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ILPR: u32, // 0x20
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IBRD: WriteOnly<u32, IBRD::Register>, // 0x24
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FBRD: WriteOnly<u32, FBRD::Register>, // 0x28
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LCRH: WriteOnly<u32, LCRH::Register>, // 0x2C
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CR: WriteOnly<u32, CR::Register>, // 0x30
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IFLS: u32, // 0x34
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IMSC: u32, // 0x38
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RIS: u32, // 0x3C
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MIS: u32, // 0x40
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ICR: WriteOnly<u32, ICR::Register>, // 0x44
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DMACR: u32, // 0x48
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__reserved_2: [u32; 14], // 0x4c-0x7c
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ITCR: u32, // 0x80
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ITIP: u32, // 0x84
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ITOP: u32, // 0x88
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TDR: u32, // 0x8C
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}
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pub enum PL011UartError {
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MailboxError,
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}
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pub type Result<T> = ::core::result::Result<T, PL011UartError>;
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pub struct PL011Uart {
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base_addr: usize,
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}
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impl ops::Deref for PL011Uart {
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type Target = RegisterBlock;
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fn deref(&self) -> &Self::Target {
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unsafe { &*self.ptr() }
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}
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}
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impl PL011Uart {
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pub fn new_default() -> PL011Uart {
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const UART0_BASE: u32 = BcmHost::get_peripheral_address() + 0x20_1000;
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PL011Uart {
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base_addr: usize::try_from(UART0_BASE).unwrap(),
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}
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}
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pub fn new(base_addr: usize) -> PL011Uart {
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PL011Uart { base_addr }
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}
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/// Returns a pointer to the register block
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fn ptr(&self) -> *const RegisterBlock {
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self.base_addr as *const _
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}
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/// Set baud rate and characteristics (115200 8N1) and map to GPIO
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pub fn init(&self, mbox: &mut mailbox::Mailbox, gpio: &gpio::GPIO) -> Result<()> {
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// turn off UART0
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self.CR.set(0);
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// set up clock for consistent divisor values
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mbox.buffer[0] = 9 * 4;
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mbox.buffer[1] = mailbox::REQUEST;
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mbox.buffer[2] = mailbox::tag::SetClockRate;
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mbox.buffer[3] = 12;
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mbox.buffer[4] = 8;
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mbox.buffer[5] = mailbox::clock::UART; // UART clock
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mbox.buffer[6] = 4_000_000; // 4Mhz
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mbox.buffer[7] = 0; // skip turbo setting
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mbox.buffer[8] = mailbox::tag::End;
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if mbox.call(mailbox::channel::PropertyTagsArmToVc).is_err() {
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return Err(PL011UartError::MailboxError); // Abort if UART clocks couldn't be set
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};
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// map UART0 to GPIO pins
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gpio.GPFSEL1
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.modify(gpio::GPFSEL1::FSEL14::TXD0 + gpio::GPFSEL1::FSEL15::RXD0);
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gpio.GPPUD.set(0); // enable pins 14 and 15
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loop_delay(150);
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gpio.GPPUDCLK0.modify(
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gpio::GPPUDCLK0::PUDCLK14::AssertClock + gpio::GPPUDCLK0::PUDCLK15::AssertClock,
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);
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loop_delay(150);
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gpio.GPPUDCLK0.set(0);
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self.ICR.write(ICR::ALL::CLEAR);
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self.IBRD.write(IBRD::IBRD.val(2)); // Results in 115200 baud
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self.FBRD.write(FBRD::FBRD.val(0xB));
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self.LCRH.write(LCRH::WLEN::EightBit); // 8N1
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self.CR
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.write(CR::UARTEN::Enabled + CR::TXE::Enabled + CR::RXE::Enabled);
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Ok(())
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}
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}
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impl Drop for PL011Uart {
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fn drop(&mut self) {
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self.CR
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.write(CR::UARTEN::Disabled + CR::TXE::Disabled + CR::RXE::Disabled);
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}
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}
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impl ConsoleOps for PL011Uart {
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/// Send a character
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fn putc(&self, c: char) {
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// wait until we can send
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loop_until(|| !self.FR.is_set(FR::TXFF));
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// write the character to the buffer
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self.DR.set(c as u32);
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}
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/// Display a string
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fn puts(&self, string: &str) {
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for c in string.chars() {
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// convert newline to carrige return + newline
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if c == '\n' {
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self.putc('\r')
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}
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self.putc(c);
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}
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}
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/// Receive a character
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fn getc(&self) -> char {
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// wait until something is in the buffer
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loop_until(|| !self.FR.is_set(FR::RXFE));
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// read it and return
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let mut ret = self.DR.get() as u8 as char;
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// convert carrige return to newline
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if ret == '\r' {
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ret = '\n'
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}
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ret
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}
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}
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