241 lines
7.0 KiB
Rust
241 lines
7.0 KiB
Rust
use arch::*;
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use core::{fmt, ops};
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use platform::{gpio, rpi3::PERIPHERAL_BASE};
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use register::mmio::*;
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// The base address for UART.
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const UART0_BASE: u32 = PERIPHERAL_BASE + 0x20_1000;
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// The offsets for reach register for the UART.
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const UART0_DR: u32 = UART0_BASE + 0x00;
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const UART0_RSRECR: u32 = UART0_BASE + 0x04;
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const UART0_FR: u32 = UART0_BASE + 0x18;
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const UART0_ILPR: u32 = UART0_BASE + 0x20;
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const UART0_IBRD: u32 = UART0_BASE + 0x24;
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const UART0_FBRD: u32 = UART0_BASE + 0x28;
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const UART0_LCRH: u32 = UART0_BASE + 0x2C;
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const UART0_CR: u32 = UART0_BASE + 0x30;
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const UART0_IFLS: u32 = UART0_BASE + 0x34;
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const UART0_IMSC: u32 = UART0_BASE + 0x38;
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const UART0_RIS: u32 = UART0_BASE + 0x3C;
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const UART0_MIS: u32 = UART0_BASE + 0x40;
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const UART0_ICR: u32 = UART0_BASE + 0x44;
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const UART0_DMACR: u32 = UART0_BASE + 0x48;
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const UART0_ITCR: u32 = UART0_BASE + 0x80;
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const UART0_ITIP: u32 = UART0_BASE + 0x84;
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const UART0_ITOP: u32 = UART0_BASE + 0x88;
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const UART0_TDR: u32 = UART0_BASE + 0x8C;
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// Mini UART
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const UART1_BASE: u32 = PERIPHERAL_BASE + 0x21_5000;
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#[allow(non_snake_case)]
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#[repr(C)]
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pub struct RegisterBlock {
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__reserved_0: u32, // 0x00 - AUX_IRQ
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AUX_ENABLES: ReadWrite<u32, AUX_ENABLES::Register>, // 0x04
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__reserved_1: [u32; 14], // 0x08
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AUX_MU_IO: ReadWrite<u32>, // 0x40 - Mini Uart I/O Data
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AUX_MU_IER: WriteOnly<u32>, // 0x44 - Mini Uart Interrupt Enable
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AUX_MU_IIR: WriteOnly<u32, AUX_MU_IIR::Register>, // 0x48
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AUX_MU_LCR: WriteOnly<u32, AUX_MU_LCR::Register>, // 0x4C
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AUX_MU_MCR: WriteOnly<u32>, // 0x50
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AUX_MU_LSR: ReadOnly<u32, AUX_MU_LSR::Register>, // 0x54
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__reserved_2: [u32; 2], // 0x58 - AUX_MU_MSR, AUX_MU_SCRATCH
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AUX_MU_CNTL: WriteOnly<u32, AUX_MU_CNTL::Register>, // 0x60
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__reserved_3: u32, // 0x64 - AUX_MU_STAT
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AUX_MU_BAUD: WriteOnly<u32, AUX_MU_BAUD::Register>, // 0x68
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}
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// Auxiliary mini UART registers
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//
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// Descriptions taken from
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// https://github.com/raspberrypi/documentation/files/1888662/BCM2837-ARM-Peripherals.-.Revised.-.V2-1.pdf
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register_bitfields! {
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u32,
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/// Auxiliary enables
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AUX_ENABLES [
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/// If set the mini UART is enabled. The UART will immediately
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/// start receiving data, especially if the UART1_RX line is
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/// low.
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/// If clear the mini UART is disabled. That also disables any
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/// mini UART register access
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MINI_UART_ENABLE OFFSET(0) NUMBITS(1) []
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],
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/// Mini Uart Interrupt Identify
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AUX_MU_IIR [
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/// Writing with bit 1 set will clear the receive FIFO
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/// Writing with bit 2 set will clear the transmit FIFO
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FIFO_CLEAR OFFSET(1) NUMBITS(2) [
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Rx = 0b01,
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Tx = 0b10,
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All = 0b11
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]
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],
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/// Mini Uart Line Control
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AUX_MU_LCR [
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/// Mode the UART works in
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DATA_SIZE OFFSET(0) NUMBITS(2) [
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SevenBit = 0b00,
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EightBit = 0b11
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]
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],
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/// Mini Uart Line Status
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AUX_MU_LSR [
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/// This bit is set if the transmit FIFO can accept at least
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/// one byte.
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TX_EMPTY OFFSET(5) NUMBITS(1) [],
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/// This bit is set if the receive FIFO holds at least 1
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/// symbol.
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DATA_READY OFFSET(0) NUMBITS(1) []
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],
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/// Mini Uart Extra Control
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AUX_MU_CNTL [
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/// If this bit is set the mini UART transmitter is enabled.
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/// If this bit is clear the mini UART transmitter is disabled.
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TX_EN OFFSET(1) NUMBITS(1) [
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Disabled = 0,
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Enabled = 1
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],
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/// If this bit is set the mini UART receiver is enabled.
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/// If this bit is clear the mini UART receiver is disabled.
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RX_EN OFFSET(0) NUMBITS(1) [
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Disabled = 0,
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Enabled = 1
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]
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],
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/// Mini Uart Baudrate
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AUX_MU_BAUD [
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/// Mini UART baudrate counter
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RATE OFFSET(0) NUMBITS(16) []
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]
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}
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pub struct MiniUart;
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/// Deref to RegisterBlock
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///
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/// Allows writing
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/// ```
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/// self.MU_IER.read()
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/// ```
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/// instead of something along the lines of
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/// ```
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/// unsafe { (*MiniUart::ptr()).MU_IER.read() }
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/// ```
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impl ops::Deref for MiniUart {
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type Target = RegisterBlock;
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fn deref(&self) -> &Self::Target {
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unsafe { &*Self::ptr() }
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}
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}
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impl MiniUart {
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pub fn new() -> MiniUart {
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MiniUart
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}
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/// Returns a pointer to the register block
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fn ptr() -> *const RegisterBlock {
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UART1_BASE as *const _
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}
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///Set baud rate and characteristics (115200 8N1) and map to GPIO
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#[cfg(not(feature = "noserial"))]
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pub fn init(&self) {
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// initialize UART
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self.AUX_ENABLES.modify(AUX_ENABLES::MINI_UART_ENABLE::SET);
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self.AUX_MU_IER.set(0);
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self.AUX_MU_CNTL.set(0);
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self.AUX_MU_LCR.write(AUX_MU_LCR::DATA_SIZE::EightBit);
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self.AUX_MU_MCR.set(0);
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self.AUX_MU_IER.set(0);
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self.AUX_MU_IIR.write(AUX_MU_IIR::FIFO_CLEAR::All);
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self.AUX_MU_BAUD.write(AUX_MU_BAUD::RATE.val(270)); // 115200 baud
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// map UART1 to GPIO pins
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unsafe {
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(*gpio::GPFSEL1).modify(gpio::GPFSEL1::FSEL14::TXD1 + gpio::GPFSEL1::FSEL15::RXD1);
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(*gpio::GPPUD).set(0); // enable pins 14 and 15
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loop_delay(150);
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(*gpio::GPPUDCLK0).write(
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gpio::GPPUDCLK0::PUDCLK14::AssertClock + gpio::GPPUDCLK0::PUDCLK15::AssertClock,
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);
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loop_delay(150);
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(*gpio::GPPUDCLK0).set(0);
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}
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self.AUX_MU_CNTL
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.write(AUX_MU_CNTL::RX_EN::Enabled + AUX_MU_CNTL::TX_EN::Enabled);
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}
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#[cfg(feature = "noserial")]
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pub fn init(&self) {}
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/// Send a character
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#[cfg(not(feature = "noserial"))]
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pub fn send(&self, c: char) {
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// wait until we can send
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loop_until(|| self.AUX_MU_LSR.is_set(AUX_MU_LSR::TX_EMPTY));
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// write the character to the buffer
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self.AUX_MU_IO.set(c as u32);
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}
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#[cfg(feature = "noserial")]
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pub fn send(&self, _c: char) {}
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/// Receive a character
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#[cfg(not(feature = "noserial"))]
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pub fn getc(&self) -> char {
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// wait until something is in the buffer
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loop_until(|| self.AUX_MU_LSR.is_set(AUX_MU_LSR::DATA_READY));
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// read it and return
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let ret = self.AUX_MU_IO.get() as u8 as char;
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// convert carriage return to newline
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if ret == '\r' {
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'\n'
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} else {
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ret
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}
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}
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#[cfg(feature = "noserial")]
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pub fn getc(&self) -> char {
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'\n'
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}
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/// Display a string
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pub fn puts(&self, string: &str) {
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for c in string.chars() {
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// convert newline to carriage return + newline
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if c == '\n' {
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self.send('\r')
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}
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self.send(c);
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}
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}
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}
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impl fmt::Write for MiniUart {
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fn write_str(&mut self, s: &str) -> fmt::Result {
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self.puts(s);
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Ok(())
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}
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}
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