608 lines
19 KiB
Rust
608 lines
19 KiB
Rust
/*
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* SPDX-License-Identifier: BlueOak-1.0.0
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* Copyright (c) Berkus Decker <berkus+vesper@metta.systems>
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*/
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//! MMU initialisation.
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//!
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//! Paging is mostly based on [previous version](https://os.phil-opp.com/page-tables/) of
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//! Phil Opp's [paging guide](https://os.phil-opp.com/paging-implementation/) and
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//! [ARMv8 ARM memory addressing](https://static.docs.arm.com/100940/0100/armv8_a_address%20translation_100940_0100_en.pdf).
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//! It includes ideas from Sergio Benitez' cs140e OSdev course material on type-safe access.
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#![allow(dead_code)]
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use {
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crate::memory::{
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page_size::{Size1GiB, Size2MiB, Size4KiB},
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PageSize,
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//virt_page::Page,
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PhysAddr,
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PhysFrame,
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VirtAddr,
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},
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core::{
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marker::PhantomData,
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ops::{Index, IndexMut},
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ptr::Unique,
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},
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cortex_a::barrier,
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register::register_bitfields,
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snafu::Snafu,
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};
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#[derive(Debug, Snafu)]
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enum MmuError {}
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pub fn init() -> Result<(), MmuError> {
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// Prepare the memory attribute indirection register.
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mair::set_up();
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// Point to the LVL2 table base address in TTBR0.
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TTBR0_EL1.set_baddr(LVL2_TABLE.entries.base_addr_u64()); // User (lo-)space addresses
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// TTBR1_EL1.set_baddr(LVL2_TABLE.entries.base_addr_u64()); // Kernel (hi-)space addresses
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// Configure various settings of stage 1 of the EL1 translation regime.
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let ips = ID_AA64MMFR0_EL1.read(ID_AA64MMFR0_EL1::PARange);
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TCR_EL1.write(
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TCR_EL1::TBI0::Ignored // @todo TBI1 also set to Ignored??
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+ TCR_EL1::IPS.val(ips) // Intermediate Physical Address Size
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// ttbr0 user memory addresses
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+ TCR_EL1::TG0::KiB_4 // 4 KiB granule
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+ TCR_EL1::SH0::Inner
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+ TCR_EL1::ORGN0::WriteBack_ReadAlloc_WriteAlloc_Cacheable
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+ TCR_EL1::IRGN0::WriteBack_ReadAlloc_WriteAlloc_Cacheable
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+ TCR_EL1::EPD0::EnableTTBR0Walks
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+ TCR_EL1::T0SZ.val(34) // ARMv8ARM Table D5-11 minimum TxSZ for starting table level 2
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// ttbr1 kernel memory addresses
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+ TCR_EL1::TG1::KiB_4 // 4 KiB granule
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+ TCR_EL1::SH1::Inner
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+ TCR_EL1::ORGN1::WriteBack_ReadAlloc_WriteAlloc_Cacheable
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+ TCR_EL1::IRGN1::WriteBack_ReadAlloc_WriteAlloc_Cacheable
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+ TCR_EL1::EPD1::EnableTTBR1Walks
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+ TCR_EL1::T1SZ.val(34), // ARMv8ARM Table D5-11 minimum TxSZ for starting table level 2
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);
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// Switch the MMU on.
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//
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// First, force all previous changes to be seen before the MMU is enabled.
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unsafe {
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barrier::isb(barrier::SY);
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}
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// use cortex_a::regs::RegisterReadWrite;
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// Enable the MMU and turn on data and instruction caching.
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SCTLR_EL1.modify(SCTLR_EL1::M::Enable + SCTLR_EL1::C::Cacheable + SCTLR_EL1::I::Cacheable);
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// Force MMU init to complete before next instruction
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/*
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* Invalidate the local I-cache so that any instructions fetched
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* speculatively from the PoC are discarded, since they may have
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* been dynamically patched at the PoU.
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*/
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unsafe {
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barrier::isb(barrier::SY);
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}
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Ok(())
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}
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/*
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* With 4k page granule, a virtual address is split into 4 lookup parts
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* spanning 9 bits each:
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*
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* _______________________________________________
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* | | | | | | |
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* | signx | Lv0 | Lv1 | Lv2 | Lv3 | off |
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* |_______|_______|_______|_______|_______|_______|
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* 63-48 47-39 38-30 29-21 20-12 11-00
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*
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* mask page size
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*
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* Lv0: FF8000000000 --
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* Lv1: 7FC0000000
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* off: 3FFFFFFF 1G
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* Lv2: 3FE00000
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* off: 1FFFFF 2M
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* Lv3: 1FF000
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* off: FFF 4K
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*
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* RPi3 supports 64K and 4K granules, also 40-bit physical addresses.
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* It also can address only 1G physical memory, so these 40-bit phys addresses are a fake.
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*
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* 48-bit virtual address space; different mappings in VBAR0 (EL0) and VBAR1 (EL1+).
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*/
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register_bitfields! {
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u64,
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VA_INDEX [
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LEVEL0 OFFSET(39) NUMBITS(9) [],
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LEVEL1 OFFSET(30) NUMBITS(9) [],
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LEVEL2 OFFSET(21) NUMBITS(9) [],
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LEVEL3 OFFSET(12) NUMBITS(9) [],
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OFFSET OFFSET(0) NUMBITS(12) []
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]
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}
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register_bitfields! {
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u64,
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// AArch64 Reference Manual page 2150, D5-2445
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TABLE_DESCRIPTOR [
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// In table descriptors
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NSTable_EL3 OFFSET(63) NUMBITS(1) [],
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/// Access Permissions for subsequent tables
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APTable OFFSET(61) NUMBITS(2) [
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RW_EL1 = 0b00,
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RW_EL1_EL0 = 0b01,
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RO_EL1 = 0b10,
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RO_EL1_EL0 = 0b11
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],
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// User execute-never for subsequent tables
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UXNTable OFFSET(60) NUMBITS(1) [
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Execute = 0,
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NeverExecute = 1
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],
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/// Privileged execute-never for subsequent tables
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PXNTable OFFSET(59) NUMBITS(1) [
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Execute = 0,
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NeverExecute = 1
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],
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// In block descriptors
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// OS-specific data
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OSData OFFSET(55) NUMBITS(4) [],
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// User execute-never
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UXN OFFSET(54) NUMBITS(1) [
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Execute = 0,
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NeverExecute = 1
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],
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/// Privileged execute-never
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PXN OFFSET(53) NUMBITS(1) [
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Execute = 0,
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NeverExecute = 1
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],
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// @fixme ?? where is this described
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CONTIGUOUS OFFSET(52) NUMBITS(1) [
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False = 0,
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True = 1
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],
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// @fixme ?? where is this described
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DIRTY OFFSET(51) NUMBITS(1) [
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False = 0,
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True = 1
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],
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/// Various address fields, depending on use case
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LVL2_OUTPUT_ADDR_4KiB OFFSET(21) NUMBITS(27) [], // [47:21]
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NEXT_LVL_TABLE_ADDR_4KiB OFFSET(12) NUMBITS(36) [], // [47:12]
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// @fixme ?? where is this described
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NON_GLOBAL OFFSET(11) NUMBITS(1) [
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False = 0,
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True = 1
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],
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/// Access flag
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AF OFFSET(10) NUMBITS(1) [
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False = 0,
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True = 1
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],
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/// Share-ability field
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SH OFFSET(8) NUMBITS(2) [
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OuterShareable = 0b10,
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InnerShareable = 0b11
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],
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/// Access Permissions
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AP OFFSET(6) NUMBITS(2) [
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RW_EL1 = 0b00,
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RW_EL1_EL0 = 0b01,
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RO_EL1 = 0b10,
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RO_EL1_EL0 = 0b11
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],
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NS_EL3 OFFSET(5) NUMBITS(1) [],
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/// Memory attributes index into the MAIR_EL1 register
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AttrIndx OFFSET(2) NUMBITS(3) [],
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TYPE OFFSET(1) NUMBITS(1) [
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Block = 0,
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Table = 1
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],
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VALID OFFSET(0) NUMBITS(1) [
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False = 0,
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True = 1
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]
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]
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}
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// type VaIndex = register::FieldValue<u64, VA_INDEX::Register>;
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type VaType = register::LocalRegisterCopy<u64, VA_INDEX::Register>;
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type EntryFlags = register::FieldValue<u64, TABLE_DESCRIPTOR::Register>;
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type EntryRegister = register::LocalRegisterCopy<u64, TABLE_DESCRIPTOR::Register>;
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// Possible mappings:
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// * TTBR0 pointing to user page global directory
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// * TTBR0 pointing to user page upper directory (only if mmu is set up differently)
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// * TTBR1 pointing to kernel page global directory with full physmem access
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// * Paging system uses a separate address space in top kernel region (TTBR1) to access
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// * entire physical memory contents.
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// * This mapping is not available to user space (user space uses TTBR0).
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// *
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// * Use the largest possible granule size to map physical memory since we want to use
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// * the least amount of memory for these mappings.
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// TTBR0 Page Global Directory
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// Level 0 descriptors can only output the address of a Level 1 table.
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// Level 3 descriptors cannot point to another table and can only output block addresses.
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// The format of the table is therefore slightly different for Level 3.
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//
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// this means:
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// - in level 0 page table can be only TableDescriptors
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// - in level 1,2 page table can be TableDescriptors, Lvl2BlockDescriptors (PageDescriptors)
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// - in level 3 page table can be only PageDescriptors
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// Level / Types | Table Descriptor | Lvl2BlockDescriptor (PageDescriptor)
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// --------------+------------------+--------------------------------------
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// 0 | X | (with 4KiB granule)
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// 1 | X | X (1GiB range)
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// 2 | X | X (2MiB range)
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// 3 | | X (4KiB range) -- called PageDescriptor
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// encoding actually the same as in Table Descriptor
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// Translation granule affects the size of the block addressed.
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// Lets use 4KiB granule on RPi3 for simplicity.
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// 1, set 4KiB granule size to use the PGD - we could use 16KiB granule instead?
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// - need to measure waste level
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// - but lets stick with 4KiB for now
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//
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// If I have, for example, Table<Level0> I can get from it N `Table<Level1>` (via impl HierarchicalTable)
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// From Table<Level1> I can get either `Table<Level2>` (via impl HierarchicalTable) or `BlockDescriptor<Size1GiB>`
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// From Table<Level2> I can get either `Table<Level3>` (via impl HierarchicalTable) or `BlockDescriptor<Size2MiB>`
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// From Table<Level3> I can only get `PageDescriptor<Size4KiB>` (because no impl HierarchicalTable exists)
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/// GlobalDirectory [ UpperDirectory entries ]
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/// UpperDirectory [ PageDirectory | GiantPage ]
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/// PageDirectory [ PageTable | LargePage ]
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/// PageTable [ PageFrames ]
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// do those as separate types, then in accessors allow only certain combinations
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// e.g.
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// struct UpperDirectoryEntry; // DirectoryEntry<L0>
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// struct PageDirectoryEntry; // DirectoryEntry<L1>
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// struct GiantPageFrame; // PageFrame<Size1GiB>
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// struct PageTableEntry; // DirectoryEntry<L2>
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// struct LargePageFrame; // PageFrame<Size2MiB>
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// struct PageFrame; // PageFrame<Size4KiB>
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// enum PageTableEntry { Page(&mut PageDescriptor), Block(&mut BlockDescriptor), Etc(&mut u64), Invalid(&mut u64) }
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// impl PageTabelEntry { fn new_from_entry_addr(&u64) }
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// return enum PageTableEntry constructed from table bits in u64
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enum L0Entries {
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UpperDirectoryEntry(VirtAddr),
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}
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enum L1Entries {
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PageDirectoryEntry(VirtAddr),
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GiantPageFrame(PhysFrame<Size1GiB>),
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}
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enum L2Entries {
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PageTableEntry(VirtAddr),
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LargePageFrame(PhysFrame<Size2MiB>),
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}
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enum L3Entries {
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PageFrame(PhysFrame<Size4KiB>),
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}
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enum Frames {
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GiantPageFrame,
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LargePageFrame,
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PageFrame,
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}
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// ----
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// ----
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// ---- Table levels
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// ----
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// ----
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/// L0 table -- only pointers to L1 tables
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pub enum L0PageGlobalDirectory {}
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/// L1 tables -- pointers to L2 tables or giant 1GiB pages
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pub enum L1PageUpperDirectory {}
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/// L2 tables -- pointers to L3 tables or huge 2MiB pages
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pub enum L2PageDirectory {}
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/// L3 tables -- only pointers to 4/16KiB pages
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pub enum L3PageTable {}
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/// Shared trait for specific table levels.
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pub trait TableLevel {}
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/// Shared trait for hierarchical table levels.
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///
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/// Specifies what is the next level of page table hierarchy.
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pub trait HierarchicalLevel: TableLevel {
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/// Level of the next translation table below this one.
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type NextLevel: TableLevel;
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// fn translate() -> Directory<NextLevel>;
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}
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/// Specify allowed page size for each level.
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pub trait HierarchicalPageLevel: TableLevel {
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/// Size of the page that can be contained in this table level.
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type PageLevel: PageSize;
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}
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impl TableLevel for L0PageGlobalDirectory {}
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impl TableLevel for L1PageUpperDirectory {}
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impl TableLevel for L2PageDirectory {}
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impl TableLevel for L3PageTable {}
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impl HierarchicalLevel for L0PageGlobalDirectory {
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type NextLevel = L1PageUpperDirectory;
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}
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impl HierarchicalLevel for L1PageUpperDirectory {
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type NextLevel = L2PageDirectory;
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}
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impl HierarchicalLevel for L2PageDirectory {
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type NextLevel = L3PageTable;
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}
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// L3PageTables do not have next level, therefore they are not HierarchicalLevel
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// L0PageGlobalDirectory does not contain pages, so they are not HierarchicalPageLevel
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impl HierarchicalPageLevel for L1PageUpperDirectory {
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type PageLevel = Size1GiB;
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}
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impl HierarchicalPageLevel for L2PageDirectory {
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type PageLevel = Size2MiB;
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}
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impl HierarchicalPageLevel for L3PageTable {
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type PageLevel = Size4KiB;
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}
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// ----
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// ----
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// ---- Directory
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// ----
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// ----
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// Maximum OA is 48 bits.
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//
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// Level 0 table descriptor has Output Address in [47:12] --> level 1 table
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// Level 0 descriptor cannot be block descriptor.
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//
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// Level 1 table descriptor has Output Address in [47:12] --> level 2 table
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// Level 1 block descriptor has Output Address in [47:30]
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//
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// Level 2 table descriptor has Output Address in [47:12] --> level 3 table
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// Level 2 block descriptor has Output Address in [47:21]
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//
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// Level 3 block descriptor has Output Address in [47:12]
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// Upper Attributes [63:51]
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// Res0 [50:48]
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// Lower Attributes [11:2]
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// 11b [1:0]
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// Each table consists of 2**9 entries
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const TABLE_BITS: usize = 9;
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const INDEX_MASK: usize = (1 << TABLE_BITS) - 1;
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static_assertions::const_assert!(INDEX_MASK == 0x1ff);
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// @todo Table in mmu.rs
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/// MMU address translation table.
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/// Contains just u64 internally, provides enum interface on top
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#[repr(C)]
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#[repr(align(4096))]
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struct Directory<Level: TableLevel> {
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entries: [u64; 1 << TABLE_BITS],
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level: PhantomData<Level>,
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}
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impl Directory<L0PageGlobalDirectory> {
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fn next(&self, address: VirtAddr) -> Option<L0Entries> {
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let va = VaType::new(address.as_u64());
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let index = va.read(VA_INDEX::LEVEL0);
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match self.next_table_address(index as usize) {
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Some(phys_addr) => Some(L0Entries::UpperDirectoryEntry(phys_addr.user_to_kernel())),
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None => None,
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}
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}
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}
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impl Directory<L1PageUpperDirectory> {
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fn next(&self, address: VirtAddr) -> Option<L1Entries> {
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let va = VaType::new(address.as_u64());
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let index = va.read(VA_INDEX::LEVEL1);
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match self.next_table_address(index as usize) {
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Some(phys_addr) => Some(L1Entries::PageDirectoryEntry(phys_addr.user_to_kernel())),
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None => None, // @todo could be 1GiB frame
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}
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}
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}
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impl Directory<L2PageDirectory> {
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fn next(&self, address: VirtAddr) -> Option<L2Entries> {
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let va = VaType::new(address.as_u64());
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let index = va.read(VA_INDEX::LEVEL2);
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match self.next_table_address(index as usize) {
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Some(phys_addr) => Some(L2Entries::PageTableEntry(phys_addr.user_to_kernel())),
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None => None, // @todo could be 2MiB frame
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}
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}
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}
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impl Directory<L3PageTable> {
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fn next(&self, address: VirtAddr) -> Option<L3Entries> {
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let va = VaType::new(address.as_u64());
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let _index = va.read(VA_INDEX::LEVEL3);
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// @fixme wrong function
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// match self.next_table_address(index as usize) {
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// Some(phys_addr) => Some(L3Entries::PageFrame(phys_addr.user_to_kernel())),
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// None => None, // Nothing there
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// }
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None
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}
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}
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// Implementation code shared for all levels of page tables
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impl<Level> Directory<Level>
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where
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Level: TableLevel,
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{
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/// Construct a zeroed table at given physical location.
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// unsafe fn at(location: PhysAddr) -> &Self {}
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/// Construct and return zeroed table.
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fn zeroed() -> Self {
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Self {
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entries: [0; 1 << TABLE_BITS],
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level: PhantomData,
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}
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}
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/// Zero out entire table.
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pub fn zero(&mut self) {
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for entry in self.entries.iter_mut() {
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*entry = 0;
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}
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}
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}
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impl<Level> Index<usize> for Directory<Level>
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where
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Level: TableLevel,
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{
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type Output = u64;
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fn index(&self, index: usize) -> &Self::Output {
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&self.entries[index]
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}
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}
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impl<Level> IndexMut<usize> for Directory<Level>
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where
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Level: TableLevel,
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{
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fn index_mut(&mut self, index: usize) -> &mut Self::Output {
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&mut self.entries[index]
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}
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}
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impl<Level> Directory<Level>
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where
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Level: HierarchicalLevel,
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{
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fn next_table_address(&self, index: usize) -> Option<PhysAddr> {
|
|
let entry_flags = EntryRegister::new(self[index]);
|
|
// If table entry has 0b11 mask set, it is a valid table entry.
|
|
// Address of the following table may be extracted from bits 47:12
|
|
if entry_flags.matches_all(TABLE_DESCRIPTOR::VALID::True + TABLE_DESCRIPTOR::TYPE::Table) {
|
|
Some(PhysAddr::new(
|
|
entry_flags.read(TABLE_DESCRIPTOR::NEXT_LVL_TABLE_ADDR_4KiB) << Size4KiB::SHIFT,
|
|
))
|
|
} else {
|
|
None
|
|
}
|
|
}
|
|
|
|
pub fn next_table(&self, index: usize) -> Option<&Directory<Level::NextLevel>> {
|
|
self.next_table_address(index)
|
|
.map(|address| unsafe { &*(address.user_to_kernel().as_ptr()) })
|
|
}
|
|
|
|
pub fn next_table_mut(&mut self, index: usize) -> Option<&mut Directory<Level::NextLevel>> {
|
|
self.next_table_address(index)
|
|
.map(|address| unsafe { &mut *(address.user_to_kernel().as_mut_ptr()) })
|
|
}
|
|
|
|
pub fn translate_levels(&self, _address: VirtAddr) -> Option<Frames> {
|
|
None
|
|
}
|
|
}
|
|
|
|
// ----
|
|
// ----
|
|
// ---- VirtSpace
|
|
// ----
|
|
// ----
|
|
|
|
/// Errors from mapping layer
|
|
#[derive(Debug, Snafu)]
|
|
pub enum TranslationError {
|
|
/// No page found. @todo
|
|
NoPage,
|
|
}
|
|
|
|
/// Virtual address space. @todo
|
|
pub struct VirtSpace {
|
|
l0: Unique<Directory<L0PageGlobalDirectory>>,
|
|
}
|
|
|
|
// translation steps:
|
|
// l0: upper page directory or Err()
|
|
// l1: lower page directory or 1Gb aperture or Err()
|
|
// l2: page table or 2MiB aperture or Err()
|
|
// l3: 4KiB aperture or Err()
|
|
|
|
impl VirtSpace {
|
|
// Translate translates address all the way down to physical address or error.
|
|
// On each level there's next_table() fn that resolves to the next level table if possible.
|
|
// pub fn translate(&self, virtual_address: VirtAddr) -> Result<PhysAddr, TranslationError> {
|
|
// // let offset = virtual_address % Self::PageLevel::SIZE as usize; // use the size of the last page?
|
|
// self.translate_page(Page::<Self::PageLevel>::containing_address(virtual_address))?
|
|
// .map(|frame, offset| frame.start_address() + offset)
|
|
// }
|
|
}
|
|
|
|
// pageglobaldirectory.translate() {
|
|
// get page index <- generic over page level (xx << (10 + (3 - level) * 9))
|
|
// return page[index]?.translate(rest);
|
|
// }
|
|
|
|
#[cfg(test)]
|
|
mod tests {
|
|
use super::*;
|
|
|
|
#[test_case]
|
|
fn table_construction() {
|
|
let mut level0_table = Directory::<L0PageGlobalDirectory>::zeroed();
|
|
let level1_table = Directory::<L1PageUpperDirectory>::zeroed();
|
|
let level2_table = Directory::<L2PageDirectory>::zeroed();
|
|
let level3_table = Directory::<L3PageTable>::zeroed();
|
|
|
|
assert!(level0_table.next_table_address(0).is_none());
|
|
|
|
// Make entry map to a level1 table
|
|
level0_table[0] = EntryFlags::from(
|
|
TABLE_DESCRIPTOR::VALID::True
|
|
+ TABLE_DESCRIPTOR::TYPE::Table
|
|
+ TABLE_DESCRIPTOR::NEXT_LVL_TABLE_ADDR_4KiB.val(0x424242),
|
|
)
|
|
.into();
|
|
|
|
assert!(level0_table.next_table_address(0).is_some());
|
|
|
|
let addr = level0_table.next_table_address(0).unwrap();
|
|
assert_eq!(addr, (0x424242 << 12));
|
|
}
|
|
}
|