Add boot code for RPi and QEMU
This commit is contained in:
Berkus Decker
parent
be3131f666
commit
f485629fb6
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@ -4,11 +4,11 @@
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* Original code distributed under MIT, additional changes are under BlueOak-1.0.0
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*/
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ENTRY(karch_start);
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ENTRY(_boot_cores);
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/* Symbols between __boot_start and __boot_end should be dropped after init is complete.
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Symbols between __ro_start and __ro_end are the kernel code.
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Symbols between __bss_start and __bss_end must be initialized to zero by r0 code in kernel.
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Symbols between __BSS_START and __BSS_END must be initialized to zero by r0 code in kernel.
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*/
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SECTIONS
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{
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@ -49,11 +49,11 @@ SECTIONS
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.bss ALIGN(8):
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{
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__bss_start = .;
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__BSS_START = .;
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*(.bss .bss.*)
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*(COMMON)
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. = ALIGN(4096); /* Align up to 4KiB */
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__bss_end = .;
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__BSS_END = .;
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}
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/DISCARD/ : { *(.comment) *(.gnu*) *(.note*) *(.eh_frame*) }
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@ -0,0 +1,204 @@
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/*
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* SPDX-License-Identifier: BlueOak-1.0.0
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*
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* Based on ideas from Jorge Aparicio, Andre Richter, Phil Oppenheimer.
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* Copyright (c) 2019 Berkus Decker <berkus+vesper@metta.systems>
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*/
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#![deny(missing_docs)]
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#![deny(warnings)]
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use {
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crate::endless_sleep,
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cortex_a::{asm, regs::*},
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};
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/// Low-level boot of the Raspberry's processor
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/// http://infocenter.arm.com/help/topic/com.arm.doc.dai0527a/DAI0527A_baremetal_boot_code_for_ARMv8_A_processors.pdf
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/// Type check the user-supplied entry function.
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#[macro_export]
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macro_rules! entry {
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($path:path) => {
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/// # Safety
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/// Only type-checks!
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#[export_name = "main"]
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pub unsafe fn __main() -> ! {
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// type check the given path
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let f: fn() -> ! = $path;
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f()
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}
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};
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}
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/// Reset function.
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///
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/// Initializes the bss section before calling into the user's `main()`.
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///
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/// # Safety
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///
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/// Totally unsafe! We're in the hardware land.
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#[link_section = ".text.boot"]
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unsafe fn reset() -> ! {
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extern "C" {
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// Boundaries of the .bss section, provided by the linker script
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static mut __BSS_START: u64;
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static mut __BSS_END: u64;
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}
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// Set stack pointer. Used in case we started in EL1.
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const STACK_START: u64 = 0x80_000;
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SP.set(STACK_START);
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// Zeroes the .bss section
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r0::zero_bss(&mut __BSS_START, &mut __BSS_END);
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extern "Rust" {
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fn main() -> !;
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}
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main()
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}
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/// Real hardware boot-up sequence.
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///
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/// Prepare and execute transition from EL2 to EL1.
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#[link_section = ".text.boot"]
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#[inline]
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fn setup_and_enter_el1_from_el2() -> ! {
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// Enable timer counter registers for EL1
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CNTHCTL_EL2.write(CNTHCTL_EL2::EL1PCEN::SET + CNTHCTL_EL2::EL1PCTEN::SET);
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// No virtual offset for reading the counters
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CNTVOFF_EL2.set(0);
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// Set EL1 execution state to AArch64
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// @todo Explain the SWIO bit (SWIO hardwired on Pi3)
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HCR_EL2.write(HCR_EL2::RW::EL1IsAarch64 + HCR_EL2::SWIO::SET);
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// Set up a simulated exception return.
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//
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// First, fake a saved program status, where all interrupts were
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// masked and SP_EL1 was used as a stack pointer.
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SPSR_EL2.write(
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SPSR_EL2::D::Masked
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+ SPSR_EL2::A::Masked
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+ SPSR_EL2::I::Masked
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+ SPSR_EL2::F::Masked
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+ SPSR_EL2::M::EL1h, // Use SP_EL1
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);
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// Second, let the link register point to reset().
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ELR_EL2.set(reset as *const () as u64);
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// Set up SP_EL1 (stack pointer), which will be used by EL1 once
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// we "return" to it.
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const STACK_START: u64 = 0x80_000;
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SP_EL1.set(STACK_START);
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// Use `eret` to "return" to EL1. This will result in execution of
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// `reset()` in EL1.
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asm::eret()
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}
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/// QEMU boot-up sequence.
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///
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/// Processors enter EL3 after reset.
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/// ref: http://infocenter.arm.com/help/topic/com.arm.doc.dai0527a/DAI0527A_baremetal_boot_code_for_ARMv8_A_processors.pdf
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/// section: 5.5.1
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/// However, GPU init code must be switching it down to EL2.
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/// QEMU can't emulate Raspberry Pi properly (no VC boot code), so it starts in EL3.
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///
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/// Prepare and execute transition from EL3 to EL1.
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/// (from https://github.com/s-matyukevich/raspberry-pi-os/blob/master/docs/lesson02/rpi-os.md)
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#[cfg(qemu)]
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#[link_section = ".text.boot"]
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#[inline]
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fn setup_and_enter_el1_from_el3() -> ! {
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use crate::arch::aarch64::regs::{ELR_EL3, SCR_EL3, SPSR_EL3};
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// Enable timer counter registers for EL1
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CNTHCTL_EL2.write(CNTHCTL_EL2::EL1PCEN::SET + CNTHCTL_EL2::EL1PCTEN::SET);
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// No virtual offset for reading the counters
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CNTVOFF_EL2.set(0);
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// Set System Control Register (EL1)
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// Make memory non-cacheable and disable MMU mapping.
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SCTLR_EL1
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.write(SCTLR_EL1::I::NonCacheable + SCTLR_EL1::C::NonCacheable + SCTLR_EL1::M::Disable);
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// Set Hypervisor Configuration Register (EL2)
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// Set EL1 execution state to AArch64
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// TODO: Explain the SWIO bit (SWIO hardwired on Pi3)
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HCR_EL2.write(HCR_EL2::RW::EL1IsAarch64 + HCR_EL2::SWIO::SET);
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{
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use crate::register::cpu::RegisterReadWrite;
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// Set Secure Configuration Register (EL3)
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SCR_EL3.write(SCR_EL3::RW::NextELIsAarch64 + SCR_EL3::NS::NonSecure);
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// Set Saved Program Status Register (EL3)
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// Set up a simulated exception return.
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//
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// First, fake a saved program status, where all interrupts were
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// masked and SP_EL1 was used as a stack pointer.
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SPSR_EL3.write(
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SPSR_EL3::D::Masked
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+ SPSR_EL3::A::Masked
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+ SPSR_EL3::I::Masked
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+ SPSR_EL3::F::Masked
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+ SPSR_EL3::M::EL1h, // Use SP_EL1
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);
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// Make the Exception Link Register (EL3) point to reset().
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ELR_EL3.set(reset as *const () as u64);
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}
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// Set up SP_EL1 (stack pointer), which will be used by EL1 once
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// we "return" to it.
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const STACK_START: u64 = 0x80_000;
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SP_EL1.set(STACK_START);
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// Use `eret` to "return" to EL1. This will result in execution of
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// `reset()` in EL1.
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asm::eret()
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}
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/// Entrypoint of the processor.
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///
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/// Parks all cores except core0 and checks if we started in EL2/EL3. If
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/// so, proceeds with setting up EL1.
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///
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/// This is invoked from the linker script, does arch-specific init
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/// and passes control to the kernel boot function reset().
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///
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/// Dissection of various RPi core boot stubs is available
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/// [here](https://leiradel.github.io/2019/01/20/Raspberry-Pi-Stubs.html).
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///
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#[no_mangle]
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#[link_section = ".text.boot"]
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pub unsafe extern "C" fn _boot_cores() -> ! {
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const CORE_0: u64 = 0;
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const CORE_MASK: u64 = 0x3;
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// Can't match values with dots in match, so use intermediate consts.
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#[cfg(qemu)]
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const EL3: u32 = CurrentEL::EL::EL3.value;
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const EL2: u32 = CurrentEL::EL::EL2.value;
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const EL1: u32 = CurrentEL::EL::EL1.value;
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if CORE_0 == MPIDR_EL1.get() & CORE_MASK {
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match CurrentEL.get() {
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#[cfg(qemu)]
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EL3 => setup_and_enter_el1_from_el3(),
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EL2 => setup_and_enter_el1_from_el2(),
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EL1 => reset(),
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_ => endless_sleep(),
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}
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}
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// if not core0 or not EL3/EL2/EL1, infinitely wait for events
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endless_sleep()
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}
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@ -1,41 +1,11 @@
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use {
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crate::kmain,
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cortex_a::{
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asm,
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regs::{RegisterReadOnly, RegisterReadWrite, MPIDR_EL1, SP},
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},
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};
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/// The entry to Rust, all things must be initialized
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/// This is invoked from the linker script, does arch-specific init
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/// and passes control to the kernel boot function kmain().
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///
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/// # Safety
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///
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/// Totally unsafe! We're in the hardware land.
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///
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#[no_mangle]
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pub unsafe extern "C" fn karch_start() -> ! {
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// Set sp to 0x80000 (just before kernel start)
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const STACK_START: u64 = 0x8_0000;
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SP.set(STACK_START);
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match read_cpu_id() {
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0 => kmain(),
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_ => endless_sleep(), // if not core0, indefinitely wait for events
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}
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}
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#[inline]
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pub fn read_cpu_id() -> u64 {
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const CORE_MASK: u64 = 0x3;
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MPIDR_EL1.get() & CORE_MASK
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}
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/*
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* SPDX-License-Identifier: BlueOak-1.0.0
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*/
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mod boot;
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#[inline]
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pub fn endless_sleep() -> ! {
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loop {
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asm::wfe();
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cortex_a::asm::wfe();
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}
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}
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/*
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* SPDX-License-Identifier: BlueOak-1.0.0
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*/
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#[cfg(target_arch = "aarch64")]
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#[macro_use]
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pub mod aarch64;
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/*
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* SPDX-License-Identifier: BlueOak-1.0.0
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*/
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#![no_std]
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#![no_main]
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pub mod arch;
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pub use arch::*;
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entry!(kmain);
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// Kernel entry point
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// arch crate is responsible for calling this
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#[inline]
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pub fn kmain() -> ! {
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endless_sleep()
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}
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