diff --git a/src/arch/aarch64/mmu.rs b/src/arch/aarch64/mmu.rs
index c4d3b70..adf7e78 100644
--- a/src/arch/aarch64/mmu.rs
+++ b/src/arch/aarch64/mmu.rs
@@ -245,5 +245,13 @@ pub unsafe fn init() {
     SCTLR_EL1.modify(SCTLR_EL1::M::Enable + SCTLR_EL1::C::Cacheable + SCTLR_EL1::I::Cacheable);
 
     // Force MMU init to complete before next instruction
-    barrier::isb(barrier::SY);
+    /*
+     * Invalidate the local I-cache so that any instructions fetched
+     * speculatively from the PoC are discarded, since they may have
+     * been dynamically patched at the PoU.
+     */
+    asm!("isb
+        ic iallu
+        dsb nsh
+        isb" :::: "volatile");
 }