diff --git a/nucleus/src/arch/aarch64/memory/mmu-experimental.rs b/nucleus/src/arch/aarch64/memory/mmu-experimental.rs
index 58804e1..bd91eab 100644
--- a/nucleus/src/arch/aarch64/memory/mmu-experimental.rs
+++ b/nucleus/src/arch/aarch64/memory/mmu-experimental.rs
@@ -332,32 +332,6 @@ impl fmt::Debug for PageTableEntry {
     }
 }*/
 
-/*
- */
-/*
- */
-/*
- */
-/*
- */
-/*
- */
-/*
- */
-/*
- */
-/*
- */
-/*
- */
-/*
- */
-
-/*
- * SPDX-License-Identifier: BSL-1.0 - todo this is from Sergio Benitez cs140e
- */
-// Abstractions for page tables.
-
 // to get L0 we must allocate a few frames from boot region allocator.
 // So, first we init the dtb, parse mem-regions from there, then init boot_info page and start mmu,
 // this part will be inited in mmu::init():
@@ -416,10 +390,3 @@ where
         self.next_table_mut(index).unwrap()
     }
 }
-
-// ORIGINAL MMU.RS CODE
-
-//static mut LVL0_TABLE: Table<PageGlobalDirectory> = Table {
-//    entries: [0; NUM_ENTRIES_4KIB],
-//    level: PhantomData,
-//};
diff --git a/nucleus/src/arch/aarch64/memory/mod.rs b/nucleus/src/arch/aarch64/memory/mod.rs
index fc2cd7d..1747c1c 100644
--- a/nucleus/src/arch/aarch64/memory/mod.rs
+++ b/nucleus/src/arch/aarch64/memory/mod.rs
@@ -38,10 +38,6 @@ pub trait FrameAllocator {
 
 // Identity-map things for now.
 //
-// > but more normal the simplest form is a table with 1024 32 bit entries starting at
-// a 0x4000 aligned address, where each entry describes a 1 Mb memory part.
-// On the rpi3 only the bottom 1024 entries are relevant as it has 1 Gb memory.
-
 // aarch64 granules and page sizes howto:
 // https://stackoverflow.com/questions/34269185/simultaneous-existence-of-different-sized-pages-on-aarch64