Start moving code to a new mmu2 module
This commit is contained in:
Berkus Decker
parent
9b5d7b14d3
commit
825806fdd7
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@ -1,70 +1,3 @@
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// 1: use Table<Level> for sure
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// 2: in tables use typed descriptors over generic u64 entries?? how to pick right type...
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// -- TableDescriptor
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// -- Lvl2BlockDescriptor
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// -- PageDescriptor
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// Use them instead of PageTableEntry
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// 3: Use PhysFrame<Size> and Page<Size> as flexible versions of various-sized pages
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// Level 0 descriptors can only output the address of a Level 1 table.
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// Level 3 descriptors cannot point to another table and can only output block addresses.
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// The format of the table is therefore slightly different for Level 3.
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//
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// this means:
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// - level 0 page table can be only TableDescriptors
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// - level 1,2 page table can be TableDescriptors, Lvl2BlockDescriptors (PageDescriptors)
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// - level 3 page table can be only PageDescriptors
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// Level / Types | Table Descriptor | Lvl2BlockDescriptor (PageDescriptor)
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// --------------+------------------+--------------------------------------
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// 0 | X | (with 4KiB granule)
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// 1 | X | X (1GiB range)
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// 2 | X | X (2MiB range)
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// 3 | | X (4KiB range) -- called PageDescriptor
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// encoding actually the same as in Table Descriptor
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// Translation granule affects the size of the block addressed.
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// Lets use 4KiB granule on RPi3 for simplicity.
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// This gives the following address format:
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//
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// Maximum OA is 48 bits.
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//
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// Level 0 descriptor cannot be block descriptor.
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// Level 0 table descriptor has Output Address in [47:12]
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//
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// Level 1 block descriptor has Output Address in [47:30]
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// Level 2 block descriptor has Output Address in [47:21]
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//
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// Level 1 table descriptor has Output Address in [47:12]
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// Level 2 table descriptor has Output Address in [47:12]
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//
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// Level 3 Page Descriptor:
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// Upper Attributes [63:51]
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// Res0 [50:48]
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// Output Address [47:12]
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// Lower Attributes [11:2]
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// 11b [1:0]
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// enum PageTableEntry { Page(&mut PageDescriptor), Block(&mut BlockDescriptor), Etc(&mut u64), Invalid(&mut u64) }
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// impl PageTabelEntry { fn new_from_entry_addr(&u64) }
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// If I have, for example, Table<Level0> I can get from it N `Table<Level1>` (via impl HierarchicalTable)
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// From Table<Level1> I can get either `Table<Level2>` (via impl HierarchicalTable) or `BlockDescriptor<Size1GiB>`
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// From Table<Level2> I can get either `Table<Level3>` (via impl HierarchicalTable) or `BlockDescriptor<Size2MiB>`
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// From Table<Level3> I can only get `PageDescriptor<Size4KiB>` (because no impl HierarchicalTable exists)
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// enum PageTableEntry { Page(&mut PageDescriptor), Block(&mut BlockDescriptor), Etc(&mut u64), Invalid(&mut u64) }
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// return enum PageTableEntry constructed from table bits in u64
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/*!
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* Paging system uses a separate address space in top kernel region (TTBR1) to access
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* entire physical memory contents.
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* This mapping is not available to user space (user space uses TTBR0).
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* Use the largest possible granule size to map physical memory since we want to use
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* the least amount of memory for these mappings.
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*/
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// Check largest VA supported, calculate physical_memory_offset
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//
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const PHYSICAL_MEMORY_OFFSET: u64 = 0xffff_8000_0000_0000; // Last 1GiB of VA space
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@ -332,37 +265,10 @@ impl fmt::Debug for PageTableEntry {
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}
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}*/
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// to get L0 we must allocate a few frames from boot region allocator.
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// So, first we init the dtb, parse mem-regions from there, then init boot_info page and start mmu,
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// this part will be inited in mmu::init():
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//pub const L0: *mut Table<PageGlobalDirectory> = &mut LVL0_TABLE as *mut _; // was Table<Level0>
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// @fixme this is for recursive page tables!!
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impl<L> Table<L>
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where
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L: HierarchicalLevel,
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{
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fn next_table_address(&self, index: usize) -> Option<usize> {
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let entry_flags = EntryRegister::new(self[index]);
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if entry_flags.matches_all(STAGE1_DESCRIPTOR::VALID::True + STAGE1_DESCRIPTOR::TYPE::Table)
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{
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let table_address = self as *const _ as usize;
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Some((table_address << 9) | (index << 12))
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} else {
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None
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}
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}
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pub fn next_table(&self, index: usize) -> Option<&Table<L::NextLevel>> {
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self.next_table_address(index)
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.map(|address| unsafe { &*(address as *const _) })
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}
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pub fn next_table_mut(&mut self, index: usize) -> Option<&mut Table<L::NextLevel>> {
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self.next_table_address(index)
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.map(|address| unsafe { &mut *(address as *mut _) })
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}
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pub fn next_table_create<A>(
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&mut self,
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index: usize,
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@ -1,16 +1,3 @@
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/*
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* SPDX-License-Identifier: MIT OR BlueOak-1.0.0
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* Copyright (c) 2018-2019 Andre Richter <andre.o.richter@gmail.com>
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* Copyright (c) Berkus Decker <berkus+vesper@metta.systems>
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* Original code distributed under MIT, additional changes are under BlueOak-1.0.0
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*/
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//! MMU initialisation.
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//!
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//! Paging is mostly based on [previous version](https://os.phil-opp.com/page-tables/) of
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//! Phil Opp's [paging guide](https://os.phil-opp.com/paging-implementation/) and
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//! [ARMv8 ARM memory addressing](https://static.docs.arm.com/100940/0100/armv8_a_address%20translation_100940_0100_en.pdf).
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use {
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crate::{
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arch::aarch64::memory::{
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@ -67,110 +54,6 @@ mod mair {
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}
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}
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register_bitfields! {
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u64,
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// AArch64 Reference Manual page 2150, D5-2445
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STAGE1_DESCRIPTOR [
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// In table descriptors
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NSTable_EL3 OFFSET(63) NUMBITS(1) [],
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/// Access Permissions for subsequent tables
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APTable OFFSET(61) NUMBITS(2) [
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RW_EL1 = 0b00,
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RW_EL1_EL0 = 0b01,
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RO_EL1 = 0b10,
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RO_EL1_EL0 = 0b11
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],
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// User execute-never for subsequent tables
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UXNTable OFFSET(60) NUMBITS(1) [
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Execute = 0,
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NeverExecute = 1
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],
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/// Privileged execute-never for subsequent tables
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PXNTable OFFSET(59) NUMBITS(1) [
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Execute = 0,
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NeverExecute = 1
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],
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// In block descriptors
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// OS-specific data
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OSData OFFSET(55) NUMBITS(4) [],
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// User execute-never
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UXN OFFSET(54) NUMBITS(1) [
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Execute = 0,
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NeverExecute = 1
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],
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/// Privileged execute-never
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PXN OFFSET(53) NUMBITS(1) [
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Execute = 0,
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NeverExecute = 1
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],
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// @fixme ?? where is this described
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CONTIGUOUS OFFSET(52) NUMBITS(1) [
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False = 0,
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True = 1
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],
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// @fixme ?? where is this described
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DIRTY OFFSET(51) NUMBITS(1) [
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False = 0,
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True = 1
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],
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/// Various address fields, depending on use case
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LVL2_OUTPUT_ADDR_4KiB OFFSET(21) NUMBITS(27) [], // [47:21]
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NEXT_LVL_TABLE_ADDR_4KiB OFFSET(12) NUMBITS(36) [], // [47:12]
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// @fixme ?? where is this described
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NON_GLOBAL OFFSET(11) NUMBITS(1) [
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False = 0,
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True = 1
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],
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/// Access flag
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AF OFFSET(10) NUMBITS(1) [
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False = 0,
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True = 1
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],
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/// Shareability field
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SH OFFSET(8) NUMBITS(2) [
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OuterShareable = 0b10,
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InnerShareable = 0b11
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],
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/// Access Permissions
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AP OFFSET(6) NUMBITS(2) [
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RW_EL1 = 0b00,
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RW_EL1_EL0 = 0b01,
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RO_EL1 = 0b10,
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RO_EL1_EL0 = 0b11
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],
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NS_EL3 OFFSET(5) NUMBITS(1) [],
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/// Memory attributes index into the MAIR_EL1 register
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AttrIndx OFFSET(2) NUMBITS(3) [],
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TYPE OFFSET(1) NUMBITS(1) [
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Block = 0,
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Table = 1
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],
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VALID OFFSET(0) NUMBITS(1) [
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False = 0,
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True = 1
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]
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]
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}
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/// A function that maps the generic memory range attributes to HW-specific
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/// attributes of the MMU.
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fn into_mmu_attributes(
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@ -210,33 +93,6 @@ fn into_mmu_attributes(
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desc
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}
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/*
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* With 4k page granule, a virtual address is split into 4 lookup parts
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* spanning 9 bits each:
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*
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* _______________________________________________
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* | | | | | | |
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* | signx | Lv0 | Lv1 | Lv2 | Lv3 | off |
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* |_______|_______|_______|_______|_______|_______|
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* 63-48 47-39 38-30 29-21 20-12 11-00
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*
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* mask page size
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*
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* Lv0: FF8000000000 --
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* Lv1: 7FC0000000 1G
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* Lv2: 3FE00000 2M
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* Lv3: 1FF000 4K
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* off: FFF
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*
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* RPi3 supports 64K and 4K granules, also 40-bit physical addresses.
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* It also can address only 1G physical memory, so these 40-bit phys addresses are a fake.
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*
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* 48-bit virtual address space; different mappings in VBAR0 (EL0) and VBAR1 (EL1+).
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*/
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/// Number of entries in a 4KiB mmu table.
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pub const NUM_ENTRIES_4KIB: u64 = 512;
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/// Trait for abstracting over the possible page sizes, 4KiB, 16KiB, 2MiB, 1GiB.
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pub trait PageSize: Copy + Eq + PartialOrd + Ord {
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/// The page size in bytes.
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@ -281,87 +137,6 @@ impl PageSize for Size2MiB {
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impl NotGiantPageSize for Size2MiB {}
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type EntryFlags = tock_registers::fields::FieldValue<u64, STAGE1_DESCRIPTOR::Register>;
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// type EntryRegister = register::LocalRegisterCopy<u64, STAGE1_DESCRIPTOR::Register>;
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/// L0 table -- only pointers to L1 tables
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pub enum PageGlobalDirectory {}
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/// L1 tables -- pointers to L2 tables or giant 1GiB pages
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pub enum PageUpperDirectory {}
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/// L2 tables -- pointers to L3 tables or huge 2MiB pages
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pub enum PageDirectory {}
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/// L3 tables -- only pointers to 4/16KiB pages
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pub enum PageTable {}
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/// Shared trait for specific table levels.
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pub trait TableLevel {}
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/// Shared trait for hierarchical table levels.
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///
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/// Specifies what is the next level of page table hierarchy.
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pub trait HierarchicalLevel: TableLevel {
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/// Level of the next translation table below this one.
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type NextLevel: TableLevel;
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}
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impl TableLevel for PageGlobalDirectory {}
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impl TableLevel for PageUpperDirectory {}
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impl TableLevel for PageDirectory {}
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impl TableLevel for PageTable {}
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impl HierarchicalLevel for PageGlobalDirectory {
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type NextLevel = PageUpperDirectory;
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}
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impl HierarchicalLevel for PageUpperDirectory {
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type NextLevel = PageDirectory;
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}
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impl HierarchicalLevel for PageDirectory {
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type NextLevel = PageTable;
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}
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// PageTables do not have next level, therefore they are not HierarchicalLevel
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/// MMU address translation table.
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/// Contains just u64 internally, provides enum interface on top
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#[repr(C)]
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#[repr(align(4096))]
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pub struct Table<L: TableLevel> {
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entries: [u64; NUM_ENTRIES_4KIB as usize],
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level: PhantomData<L>,
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}
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// Implementation code shared for all levels of page tables
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impl<L> Table<L>
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where
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L: TableLevel,
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{
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/// Zero out entire table.
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pub fn zero(&mut self) {
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for entry in self.entries.iter_mut() {
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*entry = 0;
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}
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}
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}
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impl<L> Index<usize> for Table<L>
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where
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L: TableLevel,
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{
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type Output = u64;
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fn index(&self, index: usize) -> &u64 {
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&self.entries[index]
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}
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}
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impl<L> IndexMut<usize> for Table<L>
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where
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L: TableLevel,
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{
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fn index_mut(&mut self, index: usize) -> &mut u64 {
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&mut self.entries[index]
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}
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}
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/// Type-safe enum wrapper covering Table<L>'s 64-bit entries.
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#[derive(Clone)]
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// #[repr(transparent)]
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|
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@ -0,0 +1,456 @@
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/*
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* SPDX-License-Identifier: BlueOak-1.0.0
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* Copyright (c) Berkus Decker <berkus+vesper@metta.systems>
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*/
|
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|
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//! MMU initialisation.
|
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//!
|
||||
//! Paging is mostly based on [previous version](https://os.phil-opp.com/page-tables/) of
|
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//! Phil Opp's [paging guide](https://os.phil-opp.com/paging-implementation/) and
|
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//! [ARMv8 ARM memory addressing](https://static.docs.arm.com/100940/0100/armv8_a_address%20translation_100940_0100_en.pdf).
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//! It includes ideas from Sergio Benitez' cs140e OSdev course material on type-safe access.
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use {
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crate::memory::{PhysAddr, VirtAddr},
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core::{
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marker::PhantomData,
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ops::{Index, IndexMut},
|
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ptr::Unique,
|
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},
|
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snafu::Snafu,
|
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};
|
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|
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/*
|
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* With 4k page granule, a virtual address is split into 4 lookup parts
|
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* spanning 9 bits each:
|
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*
|
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* _______________________________________________
|
||||
* | | | | | | |
|
||||
* | signx | Lv0 | Lv1 | Lv2 | Lv3 | off |
|
||||
* |_______|_______|_______|_______|_______|_______|
|
||||
* 63-48 47-39 38-30 29-21 20-12 11-00
|
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*
|
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* mask page size
|
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*
|
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* Lv0: FF8000000000 --
|
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* Lv1: 7FC0000000
|
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* off: 3FFFFFFF 1G
|
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* Lv2: 3FE00000
|
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* off: 1FFFFF 2M
|
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* Lv3: 1FF000
|
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* off: FFF 4K
|
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*
|
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* RPi3 supports 64K and 4K granules, also 40-bit physical addresses.
|
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* It also can address only 1G physical memory, so these 40-bit phys addresses are a fake.
|
||||
*
|
||||
* 48-bit virtual address space; different mappings in VBAR0 (EL0) and VBAR1 (EL1+).
|
||||
*/
|
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|
||||
register_bitfields! {
|
||||
u64,
|
||||
// AArch64 Reference Manual page 2150, D5-2445
|
||||
TABLE_DESCRIPTOR [
|
||||
// In table descriptors
|
||||
|
||||
NSTable_EL3 OFFSET(63) NUMBITS(1) [],
|
||||
|
||||
/// Access Permissions for subsequent tables
|
||||
APTable OFFSET(61) NUMBITS(2) [
|
||||
RW_EL1 = 0b00,
|
||||
RW_EL1_EL0 = 0b01,
|
||||
RO_EL1 = 0b10,
|
||||
RO_EL1_EL0 = 0b11
|
||||
],
|
||||
|
||||
// User execute-never for subsequent tables
|
||||
UXNTable OFFSET(60) NUMBITS(1) [
|
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Execute = 0,
|
||||
NeverExecute = 1
|
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],
|
||||
|
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/// Privileged execute-never for subsequent tables
|
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PXNTable OFFSET(59) NUMBITS(1) [
|
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Execute = 0,
|
||||
NeverExecute = 1
|
||||
],
|
||||
|
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// In block descriptors
|
||||
|
||||
// OS-specific data
|
||||
OSData OFFSET(55) NUMBITS(4) [],
|
||||
|
||||
// User execute-never
|
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UXN OFFSET(54) NUMBITS(1) [
|
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Execute = 0,
|
||||
NeverExecute = 1
|
||||
],
|
||||
|
||||
/// Privileged execute-never
|
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PXN OFFSET(53) NUMBITS(1) [
|
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Execute = 0,
|
||||
NeverExecute = 1
|
||||
],
|
||||
|
||||
// @fixme ?? where is this described
|
||||
CONTIGUOUS OFFSET(52) NUMBITS(1) [
|
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False = 0,
|
||||
True = 1
|
||||
],
|
||||
|
||||
// @fixme ?? where is this described
|
||||
DIRTY OFFSET(51) NUMBITS(1) [
|
||||
False = 0,
|
||||
True = 1
|
||||
],
|
||||
|
||||
/// Various address fields, depending on use case
|
||||
LVL2_OUTPUT_ADDR_4KiB OFFSET(21) NUMBITS(27) [], // [47:21]
|
||||
NEXT_LVL_TABLE_ADDR_4KiB OFFSET(12) NUMBITS(36) [], // [47:12]
|
||||
|
||||
// @fixme ?? where is this described
|
||||
NON_GLOBAL OFFSET(11) NUMBITS(1) [
|
||||
False = 0,
|
||||
True = 1
|
||||
],
|
||||
|
||||
/// Access flag
|
||||
AF OFFSET(10) NUMBITS(1) [
|
||||
False = 0,
|
||||
True = 1
|
||||
],
|
||||
|
||||
/// Share-ability field
|
||||
SH OFFSET(8) NUMBITS(2) [
|
||||
OuterShareable = 0b10,
|
||||
InnerShareable = 0b11
|
||||
],
|
||||
|
||||
/// Access Permissions
|
||||
AP OFFSET(6) NUMBITS(2) [
|
||||
RW_EL1 = 0b00,
|
||||
RW_EL1_EL0 = 0b01,
|
||||
RO_EL1 = 0b10,
|
||||
RO_EL1_EL0 = 0b11
|
||||
],
|
||||
|
||||
NS_EL3 OFFSET(5) NUMBITS(1) [],
|
||||
|
||||
/// Memory attributes index into the MAIR_EL1 register
|
||||
AttrIndx OFFSET(2) NUMBITS(3) [],
|
||||
|
||||
TYPE OFFSET(1) NUMBITS(1) [
|
||||
Block = 0,
|
||||
Table = 1
|
||||
],
|
||||
|
||||
VALID OFFSET(0) NUMBITS(1) [
|
||||
False = 0,
|
||||
True = 1
|
||||
]
|
||||
]
|
||||
}
|
||||
|
||||
type EntryFlags = register::FieldValue<u64, TABLE_DESCRIPTOR::Register>;
|
||||
// type EntryRegister = register::LocalRegisterCopy<u64, TABLE_DESCRIPTOR::Register>;
|
||||
|
||||
// Possible mappings:
|
||||
// * TTBR0 pointing to user page global directory
|
||||
// * TTBR0 pointing to user page upper directory (only if mmu is set up differently)
|
||||
// * TTBR1 pointing to kernel page global directory with full physmem access
|
||||
|
||||
/*!
|
||||
* Paging system uses a separate address space in top kernel region (TTBR1) to access
|
||||
* entire physical memory contents.
|
||||
* This mapping is not available to user space (user space uses TTBR0).
|
||||
*
|
||||
* Use the largest possible granule size to map physical memory since we want to use
|
||||
* the least amount of memory for these mappings.
|
||||
*/
|
||||
|
||||
// TTBR0 Page Global Directory
|
||||
|
||||
// Level 0 descriptors can only output the address of a Level 1 table.
|
||||
// Level 3 descriptors cannot point to another table and can only output block addresses.
|
||||
// The format of the table is therefore slightly different for Level 3.
|
||||
//
|
||||
// this means:
|
||||
// - in level 0 page table can be only TableDescriptors
|
||||
// - in level 1,2 page table can be TableDescriptors, Lvl2BlockDescriptors (PageDescriptors)
|
||||
// - in level 3 page table can be only PageDescriptors
|
||||
|
||||
// Level / Types | Table Descriptor | Lvl2BlockDescriptor (PageDescriptor)
|
||||
// --------------+------------------+--------------------------------------
|
||||
// 0 | X | (with 4KiB granule)
|
||||
// 1 | X | X (1GiB range)
|
||||
// 2 | X | X (2MiB range)
|
||||
// 3 | | X (4KiB range) -- called PageDescriptor
|
||||
// encoding actually the same as in Table Descriptor
|
||||
|
||||
// Translation granule affects the size of the block addressed.
|
||||
// Lets use 4KiB granule on RPi3 for simplicity.
|
||||
|
||||
// 1, set 4KiB granule size to use the PGD - we could use 16KiB granule instead?
|
||||
// - need to measure waste level
|
||||
// - but lets stick with 4KiB for now
|
||||
//
|
||||
|
||||
// If I have, for example, Table<Level0> I can get from it N `Table<Level1>` (via impl HierarchicalTable)
|
||||
// From Table<Level1> I can get either `Table<Level2>` (via impl HierarchicalTable) or `BlockDescriptor<Size1GiB>`
|
||||
// From Table<Level2> I can get either `Table<Level3>` (via impl HierarchicalTable) or `BlockDescriptor<Size2MiB>`
|
||||
// From Table<Level3> I can only get `PageDescriptor<Size4KiB>` (because no impl HierarchicalTable exists)
|
||||
|
||||
/// GlobalDirectory [ UpperDirectory entries ]
|
||||
/// UpperDirectory [ PageDirectory | GiantPage ]
|
||||
/// PageDirectory [ PageTable | LargePage ]
|
||||
/// PageTable [ PageFrames ]
|
||||
|
||||
// do those as separate types, then in accessors allow only certain combinations
|
||||
// e.g.
|
||||
// struct UpperDirectoryEntry; // DirectoryEntry<L0>
|
||||
// struct PageDirectoryEntry; // DirectoryEntry<L1>
|
||||
// struct GiantPageFrame; // PageFrame<Size1GiB>
|
||||
// struct PageTableEntry; // DirectoryEntry<L2>
|
||||
// struct LargePageFrame; // PageFrame<Size2MiB>
|
||||
// struct PageFrame; // PageFrame<Size4KiB>
|
||||
|
||||
// enum PageTableEntry { Page(&mut PageDescriptor), Block(&mut BlockDescriptor), Etc(&mut u64), Invalid(&mut u64) }
|
||||
// impl PageTabelEntry { fn new_from_entry_addr(&u64) }
|
||||
// return enum PageTableEntry constructed from table bits in u64
|
||||
|
||||
enum L0Entries {
|
||||
UpperDirectoryEntry,
|
||||
}
|
||||
enum L1Entries {
|
||||
PageDirectoryEntry,
|
||||
GiantPageFrame,
|
||||
}
|
||||
enum L2Entries {
|
||||
PageTableEntry,
|
||||
LargePageFrame,
|
||||
}
|
||||
enum L3Entries {
|
||||
PageFrame,
|
||||
}
|
||||
|
||||
// ----
|
||||
// ----
|
||||
// ---- Table levels
|
||||
// ----
|
||||
// ----
|
||||
|
||||
/// L0 table -- only pointers to L1 tables
|
||||
pub enum L0PageGlobalDirectory {}
|
||||
/// L1 tables -- pointers to L2 tables or giant 1GiB pages
|
||||
pub enum L1PageUpperDirectory {}
|
||||
/// L2 tables -- pointers to L3 tables or huge 2MiB pages
|
||||
pub enum L2PageDirectory {}
|
||||
/// L3 tables -- only pointers to 4/16KiB pages
|
||||
pub enum L3PageTable {}
|
||||
|
||||
/// Shared trait for specific table levels.
|
||||
pub trait TableLevel {}
|
||||
|
||||
/// Shared trait for hierarchical table levels.
|
||||
///
|
||||
/// Specifies what is the next level of page table hierarchy.
|
||||
pub trait HierarchicalLevel: TableLevel {
|
||||
/// Level of the next translation table below this one.
|
||||
type NextLevel: TableLevel;
|
||||
|
||||
// fn translate() -> Directory<NextLevel>;
|
||||
}
|
||||
|
||||
impl TableLevel for L0PageGlobalDirectory {}
|
||||
impl TableLevel for L1PageUpperDirectory {}
|
||||
impl TableLevel for L2PageDirectory {}
|
||||
impl TableLevel for L3PageTable {}
|
||||
|
||||
impl HierarchicalLevel for L0PageGlobalDirectory {
|
||||
type NextLevel = L1PageUpperDirectory;
|
||||
}
|
||||
impl HierarchicalLevel for L1PageUpperDirectory {
|
||||
type NextLevel = L2PageDirectory;
|
||||
}
|
||||
impl HierarchicalLevel for L2PageDirectory {
|
||||
type NextLevel = L3PageTable;
|
||||
}
|
||||
// L3PageTables do not have next level, therefore they are not HierarchicalLevel
|
||||
|
||||
// L0PageGlobalDirectory does not contain pages, so they are not HierarchicalPageLevel
|
||||
impl HierarchicalPageLevel for L1PageUpperDirectory {
|
||||
type PageLevel = Page<Size1GiB>;
|
||||
}
|
||||
impl HierarchicalPageLevel for L2PageDirectory {
|
||||
type PageLevel = Page<Size2MiB>;
|
||||
}
|
||||
impl HierarchicalPageLevel for L3PageTable {
|
||||
type PageLevel = Page<Size4KiB>;
|
||||
}
|
||||
|
||||
// ----
|
||||
// ----
|
||||
// ---- Directory
|
||||
// ----
|
||||
// ----
|
||||
|
||||
// Maximum OA is 48 bits.
|
||||
//
|
||||
// Level 0 table descriptor has Output Address in [47:12] --> level 1 table
|
||||
// Level 0 descriptor cannot be block descriptor.
|
||||
//
|
||||
// Level 1 table descriptor has Output Address in [47:12] --> level 2 table
|
||||
// Level 1 block descriptor has Output Address in [47:30]
|
||||
//
|
||||
// Level 2 table descriptor has Output Address in [47:12] --> level 3 table
|
||||
// Level 2 block descriptor has Output Address in [47:21]
|
||||
//
|
||||
// Level 3 block descriptor has Output Address in [47:12]
|
||||
// Upper Attributes [63:51]
|
||||
// Res0 [50:48]
|
||||
// Lower Attributes [11:2]
|
||||
// 11b [1:0]
|
||||
|
||||
// Each table consists of 2**9 entries
|
||||
const TABLE_BITS: usize = 9;
|
||||
const INDEX_MASK: usize = (1 << TABLE_BITS) - 1;
|
||||
|
||||
static_assert!(INDEX_MASK == 0x1ff);
|
||||
|
||||
// @todo Table in mmu.rs
|
||||
/// MMU address translation table.
|
||||
/// Contains just u64 internally, provides enum interface on top
|
||||
#[repr(C)]
|
||||
#[repr(align(4096))]
|
||||
struct Directory<Level: TableLevel> {
|
||||
entries: [u64; 1 << TABLE_BITS],
|
||||
level: PhantomData<Level>,
|
||||
}
|
||||
|
||||
// Implementation code shared for all levels of page tables
|
||||
impl<Level> Directory<Level>
|
||||
where
|
||||
Level: TableLevel,
|
||||
{
|
||||
/// Construct a zeroed table at given physical location.
|
||||
// unsafe fn at(location: PhysAddr) -> &Self {}
|
||||
|
||||
/// Construct and return zeroed table.
|
||||
fn zeroed() -> Self {
|
||||
Self {
|
||||
entries: [0; 1 << TABLE_BITS],
|
||||
level: PhantomData,
|
||||
}
|
||||
}
|
||||
|
||||
/// Zero out entire table.
|
||||
pub fn zero(&mut self) {
|
||||
for entry in self.entries.iter_mut() {
|
||||
*entry = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl<Level> Index<usize> for Directory<Level>
|
||||
where
|
||||
Level: TableLevel,
|
||||
{
|
||||
type Output = u64;
|
||||
|
||||
fn index(&self, index: usize) -> &Self::Output {
|
||||
&self.entries[index]
|
||||
}
|
||||
}
|
||||
|
||||
impl<Level> IndexMut<usize> for Directory<Level>
|
||||
where
|
||||
Level: TableLevel,
|
||||
{
|
||||
fn index_mut(&mut self, index: usize) -> &mut Self::Output {
|
||||
&mut self.entries[index]
|
||||
}
|
||||
}
|
||||
|
||||
impl<Level> Directory<Level>
|
||||
where
|
||||
Level: HierarchicalLevel,
|
||||
{
|
||||
fn next_table_address(&self, index: usize) -> Option<usize> {
|
||||
let entry_flags = EntryRegister::new(self[index]);
|
||||
// If table entry has 0b11 mask set, it is a valid table entry.
|
||||
// Address of the following table may be extracted from bits 47:12
|
||||
if entry_flags.matches_all(TABLE_DESCRIPTOR::VALID::True + TABLE_DESCRIPTOR::TYPE::Table) {
|
||||
Some(entry_flags.read(NEXT_LVL_TABLE_ADDR_4KiB) << Page4KiB::SHIFT)
|
||||
} else {
|
||||
None
|
||||
}
|
||||
}
|
||||
|
||||
pub fn next_table(&self, index: usize) -> Option<&Table<Level::NextLevel>> {
|
||||
self.next_table_address(index)
|
||||
.map(|address| unsafe { &*(address as *const _) })
|
||||
}
|
||||
|
||||
pub fn next_table_mut(&mut self, index: usize) -> Option<&mut Table<Level::NextLevel>> {
|
||||
self.next_table_address(index)
|
||||
.map(|address| unsafe { &mut *(address as *mut _) })
|
||||
}
|
||||
}
|
||||
|
||||
// ----
|
||||
// ----
|
||||
// ---- VirtSpace
|
||||
// ----
|
||||
// ----
|
||||
|
||||
pub struct VirtSpace {
|
||||
l0: Unique<Directory<L0PageGlobalDirectory>>,
|
||||
}
|
||||
|
||||
// translation steps:
|
||||
// l0: upper page directory or Err()
|
||||
// l1: lower page directory or 1Gb aperture or Err()
|
||||
// l2: page table or 2MiB aperture or Err()
|
||||
// l3: 4KiB aperture or Err()
|
||||
|
||||
impl VirtSpace {
|
||||
// Translate translates address all the way down to physical address or error.
|
||||
// On each level there's next_table() fn that resolves to the next level table if possible.
|
||||
pub fn translate(&self, virtual_address: VirtAddr) -> Result<PhysAddr, TranslationError> {
|
||||
// let offset = virtual_address % Self::PageLevel::SIZE as usize; // use the size of the last page?
|
||||
self.translate_page(Self::PageLevel::containing_address(virtual_address))?
|
||||
.map(|frame, offset| frame.start_address() + offset)
|
||||
}
|
||||
}
|
||||
|
||||
// pageglobaldirectory.translate() {
|
||||
// get page index <- generic over page level (xx << (10 + (3 - level) * 9))
|
||||
// return page[index]?.translate(rest);
|
||||
// }
|
||||
|
||||
#[cfg(test)]
|
||||
mod tests {
|
||||
use super::*;
|
||||
|
||||
#[test_case]
|
||||
fn table_construction() {
|
||||
let mut level0_table = Directory::<L0PageGlobalDirectory>::zeroed();
|
||||
let level1_table = Directory::<L1PageUpperDirectory>::zeroed();
|
||||
let level2_table = Directory::<L2PageDirectory>::zeroed();
|
||||
let level3_table = Directory::<L3PageTable>::zeroed();
|
||||
|
||||
assert!(level0_table.next_table_address(0).is_none());
|
||||
|
||||
// Make entry map to a level1 table
|
||||
level0_table[0] = EntryFlags::from(
|
||||
TABLE_DESCRIPTOR::VALID::True
|
||||
+ TABLE_DESCRIPTOR::TYPE::Table
|
||||
+ TABLE_DESCRIPTOR::NEXT_LVL_TABLE_ADDR_4KiB.val(0x424242),
|
||||
)
|
||||
.into();
|
||||
|
||||
assert!(level0_table.next_table_address(0).is_some());
|
||||
|
||||
let addr = level0_table.next_table_address(0).unwrap();
|
||||
assert_eq!(addr, (0x424242 << 12));
|
||||
}
|
||||
}
|
||||
|
|
@ -11,13 +11,13 @@ use {
|
|||
};
|
||||
|
||||
mod addr;
|
||||
pub mod mmu;
|
||||
// pub mod mmu;
|
||||
mod features;
|
||||
mod phys_frame;
|
||||
mod virt_page;
|
||||
|
||||
pub mod mmu_experimental;
|
||||
pub use mmu_experimental::*;
|
||||
pub mod mmu2;
|
||||
pub use mmu2::*;
|
||||
|
||||
// mod area_frame_allocator;
|
||||
// pub use self::area_frame_allocator::AreaFrameAllocator;
|
||||
|
|
|
|||
Loading…
Reference in New Issue