From 80ab7d9fa683f3251b7bec3469eac0cca738da3e Mon Sep 17 00:00:00 2001
From: Berkus Decker <berkus+github@metta.systems>
Date: Tue, 15 Jan 2019 00:28:56 +0200
Subject: [PATCH] Add GPIO module

---
 Cargo.toml           |  1 +
 src/platform/gpio.rs | 97 ++++++++++++++++++++++++++++++++++++++++++++
 src/platform/mod.rs  |  1 +
 3 files changed, 99 insertions(+)
 create mode 100644 src/platform/gpio.rs

diff --git a/Cargo.toml b/Cargo.toml
index 88f0b21..1ec80e8 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -25,6 +25,7 @@ rlibc = "1.0.0"
 bitflags = "1.0.1"
 register = "0.2"
 cortex-a = "2.2"
+#embedded-serial = "0.5.0"
 
 [profile.dev]
 panic = "abort"
diff --git a/src/platform/gpio.rs b/src/platform/gpio.rs
new file mode 100644
index 0000000..629f771
--- /dev/null
+++ b/src/platform/gpio.rs
@@ -0,0 +1,97 @@
+use platform::rpi3::PERIPHERAL_BASE;
+use register::mmio::*;
+
+const GPIO_BASE: u32 = PERIPHERAL_BASE + 0x20_0000;
+
+// The offsets for reach register.
+// From https://wiki.osdev.org/Raspberry_Pi_Bare_Bones
+
+//const GPFSEL0: u32 = GPIO_BASE + 0x00;
+//const GPFSEL2: u32 = GPIO_BASE + 0x08;
+//const GPFSEL3: u32 = GPIO_BASE + 0x0C;
+//const GPFSEL4: u32 = GPIO_BASE + 0x10;
+//const GPFSEL5: u32 = GPIO_BASE + 0x14;
+//const GPSET0: u32 = GPIO_BASE + 0x1C;
+//const GPSET1: u32 = GPIO_BASE + 0x20;
+//const GPCLR0: u32 = GPIO_BASE + 0x28;
+//const GPLEV0: u32 = GPIO_BASE + 0x34;
+//const GPLEV1: u32 = GPIO_BASE + 0x38;
+//const GPEDS0: u32 = GPIO_BASE + 0x40;
+//const GPEDS1: u32 = GPIO_BASE + 0x44;
+//const GPHEN0: u32 = GPIO_BASE + 0x64;
+//const GPHEN1: u32 = GPIO_BASE + 0x68;
+//
+//const GPPUDCLK1: u32 = GPIO_BASE + 0x9C;
+
+/*
+ * MIT License
+ *
+ * Copyright (c) 2018 Andre Richter <andre.o.richter@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+// Descriptions taken from
+// https://github.com/raspberrypi/documentation/files/1888662/BCM2837-ARM-Peripherals.-.Revised.-.V2-1.pdf
+register_bitfields! {
+    u32,
+
+    /// GPIO Function Select 1
+    GPFSEL1 [
+        /// Pin 15
+        FSEL15 OFFSET(15) NUMBITS(3) [
+            Input = 0b000,
+            Output = 0b001,
+            RXD1 = 0b010  // Mini UART - Alternate function 5
+
+        ],
+
+        /// Pin 14
+        FSEL14 OFFSET(12) NUMBITS(3) [
+            Input = 0b000,
+            Output = 0b001,
+            TXD1 = 0b010  // Mini UART - Alternate function 5
+        ]
+    ],
+
+    /// GPIO Pull-up/down Clock Register 0
+    GPPUDCLK0 [
+        /// Pin 15
+        PUDCLK15 OFFSET(15) NUMBITS(1) [
+            NoEffect = 0,
+            AssertClock = 1
+        ],
+
+        /// Pin 14
+        PUDCLK14 OFFSET(14) NUMBITS(1) [
+            NoEffect = 0,
+            AssertClock = 1
+        ]
+    ]
+}
+
+pub const GPFSEL1: *const ReadWrite<u32, GPFSEL1::Register> =
+    (GPIO_BASE + 0x04) as *const ReadWrite<u32, GPFSEL1::Register>;
+
+/// Controls actuation of pull up/down to ALL GPIO pins.
+pub const GPPUD: *const ReadWrite<u32> = (GPIO_BASE + 0x94) as *const ReadWrite<u32>;
+
+/// Controls actuation of pull up/down for specific GPIO pin.
+pub const GPPUDCLK0: *const ReadWrite<u32, GPPUDCLK0::Register> =
+    (GPIO_BASE + 0x98) as *const ReadWrite<u32, GPPUDCLK0::Register>;
diff --git a/src/platform/mod.rs b/src/platform/mod.rs
index 11bf6e8..63832f5 100644
--- a/src/platform/mod.rs
+++ b/src/platform/mod.rs
@@ -1 +1,2 @@
+pub mod gpio;
 pub mod rpi3;