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Use boot code from japaric/andre-richter

This commit is contained in:
Berkus Decker 2019-01-17 19:39:34 +02:00
parent e81c6ddf84
commit 67b3b95d9a
6 changed files with 221 additions and 47 deletions
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5
.cargo/config
View File

@ -1 +1,6 @@
[target.aarch64-vesper-metta]
rustflags = [
"-C", "target-feature=-fp-armv8",
"-C", "target-cpu=cortex-a53",
]

2
Cargo.toml
View File

@ -21,7 +21,9 @@ realtime = []
#crate-type = ["staticlib"]
[dependencies]
r0 = "0.2.2"
rlibc = "1.0.0"
panic-abort = "0.3.1"
bitflags = "1.0.1"
register = "0.2"
cortex-a = "2.2"

91
linker/aarch64.ld
View File

@ -1,31 +1,80 @@
ENTRY(karch_start)
OUTPUT_ARCH(aarch64)
/*OUTPUT_FORMAT(binary) Cannot change output format whilst linking AArch64 binaries.*/
/*
* MIT License
*
* Copyright (c) 2018 Andre Richter <andre.o.richter@gmail.com>
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
START_ADDRESS = 0x80000; /* AArch64 boot address is 0x80000 */
ENTRY(_boot_cores);
SECTIONS {
.text START_ADDRESS : AT(START_ADDRESS) {
*(.text.karch_start)
*(.text*)
SECTIONS
{
. = 0x80000; /* AArch64 boot address is 0x80000 */
__ro_start = .;
.text :
{
KEEP(*(.text.boot)) *(.text .text.*)
}
.rodata ALIGN (4) : {
*(.rodata*)
.vectors ALIGN(2048):
{
*(.vectors)
}
.rodata ALIGN(4):
{
*(.rodata .rodata.*)
FILL(0x00)
}
. = ALIGN(4096); /* Fill up to 4KiB */
__ro_end = .;
.data :
{
*(.data .data.*)
FILL(0x00)
}
.data ALIGN (4) : {
*(.data*)
FILL(0x00)
.bss ALIGN(8):
{
__bss_start = .;
*(.bss .bss.*)
*(COMMON)
__bss_end = .;
}
.bss ALIGN (4) : {
*(COMMON*)
*(.bss*)
}
/DISCARD/ : {
*(.comment .note* .dtors)
}
/DISCARD/ : { *(.comment) *(.gnu*) *(.note*) *(.eh_frame*) }
}
/*PROVIDE(current_el0_synchronous = default_exception_handler);
PROVIDE(current_el0_irq = default_exception_handler);
PROVIDE(current_el0_serror = default_exception_handler);
PROVIDE(current_elx_synchronous = default_exception_handler);
PROVIDE(current_elx_irq = default_exception_handler);
PROVIDE(current_elx_serror = default_exception_handler);
PROVIDE(lower_aarch64_synchronous = default_exception_handler);
PROVIDE(lower_aarch64_irq = default_exception_handler);
PROVIDE(lower_aarch64_serror = default_exception_handler);
PROVIDE(lower_aarch32_synchronous = default_exception_handler);
PROVIDE(lower_aarch32_irq = default_exception_handler);
PROVIDE(lower_aarch32_serror = default_exception_handler);*/

136
src/arch/aarch64/boot.rs Normal file
View File

@ -0,0 +1,136 @@
/*
* MIT License
*
* Copyright (c) 2018 Jorge Aparicio
* Copyright (c) 2018-2019 Andre Richter <andre.o.richter@gmail.com>
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#![deny(missing_docs)]
#![deny(warnings)]
//! Low-level boot of the Raspberry's processor
extern crate panic_abort;
/// Type check the user-supplied entry function.
#[macro_export]
macro_rules! entry {
($path:path) => {
#[export_name = "main"]
pub unsafe fn __main() -> ! {
// type check the given path
let f: fn() -> ! = $path;
f()
}
};
}
/// Reset function.
///
/// Initializes the bss section before calling into the user's `main()`.
unsafe fn reset() -> ! {
extern "C" {
// Boundaries of the .bss section, provided by the linker script
static mut __bss_start: u64;
static mut __bss_end: u64;
}
use cortex_a::regs::*;
const STACK_START: u64 = 0x80_000;
SP.set(STACK_START);
// Zeroes the .bss section
r0::zero_bss(&mut __bss_start, &mut __bss_end);
extern "Rust" {
fn main() -> !;
}
main()
}
/// Prepare and execute transition from EL2 to EL1.
#[inline]
fn setup_and_enter_el1_from_el2() -> ! {
use cortex_a::{asm, regs::*};
const STACK_START: u64 = 0x80_000;
// Enable timer counter registers for EL1
CNTHCTL_EL2.write(CNTHCTL_EL2::EL1PCEN::SET + CNTHCTL_EL2::EL1PCTEN::SET);
// No offset for reading the counters
CNTVOFF_EL2.set(0);
// Set EL1 execution state to AArch64
// TODO: Explain the SWIO bit
HCR_EL2.write(HCR_EL2::RW::EL1IsAarch64 + HCR_EL2::SWIO::SET);
// Set up a simulated exception return.
//
// First, fake a saved program status, where all interrupts were
// masked and SP_EL1 was used as a stack pointer.
SPSR_EL2.write(
SPSR_EL2::D::Masked
+ SPSR_EL2::A::Masked
+ SPSR_EL2::I::Masked
+ SPSR_EL2::F::Masked
+ SPSR_EL2::M::EL1h,
);
// Second, let the link register point to reset().
ELR_EL2.set(reset as *const () as u64);
// Set up SP_EL1 (stack pointer), which will be used by EL1 once
// we "return" to it.
SP_EL1.set(STACK_START);
// Use `eret` to "return" to EL1. This will result in execution of
// `reset()` in EL1.
asm::eret()
}
/// Entrypoint of the processor.
///
/// Parks all cores except core0 and checks if we started in EL2. If
/// so, proceeds with setting up EL1.
///
/// This is invoked from the linker script, does arch-specific init
/// and passes control to the kernel boot function main().
#[link_section = ".text.boot"]
#[no_mangle]
pub unsafe extern "C" fn _boot_cores() -> ! {
use cortex_a::{asm, regs::*};
const CORE_0: u64 = 0;
const CORE_MASK: u64 = 0x3;
const EL2: u32 = CurrentEL::EL::EL2.value;
if (CORE_0 == MPIDR_EL1.get() & CORE_MASK) && (EL2 == CurrentEL.get()) {
setup_and_enter_el1_from_el2()
}
// if not core0 or EL != 2, infinitely wait for events
loop {
asm::wfe();
}
}

18
src/arch/aarch64/mod.rs
View File

@ -1,23 +1,9 @@
// mod arch::aarch64
mod boot;
use cortex_a::{asm, barrier, regs::*};
/// The entry to Rust, all things must be initialized
/// This is invoked from the linker script, does arch-specific init
/// and passes control to the kernel boot function kmain().
#[no_mangle]
pub unsafe extern "C" fn karch_start() -> ! {
// Set sp to 0x80000 (just before kernel start)
const STACK_START: u64 = 0x8_0000;
SP.set(STACK_START);
match read_cpu_id() {
0 => ::kmain(),
_ => endless_sleep(), // if not core0, indefinitely wait for events
}
}
// Data memory barrier
#[inline]
pub fn dmb() {

16
src/main.rs
View File

@ -15,14 +15,13 @@ use architecture_not_supported_sorry;
// use core::intrinsics::abort;
#[macro_use]
// #[macro_use]
extern crate bitflags;
#[macro_use]
extern crate register;
extern crate cortex_a;
extern crate rlibc;
use core::panic::PanicInfo;
#[macro_use]
pub mod arch;
pub use arch::*;
@ -41,15 +40,9 @@ use platform::{
// Actual interfaces to call these syscalls are in vesper-user (similar to libsel4)
// pub mod vesper; -- exported from vesper-user
#[panic_handler]
fn panic(_info: &PanicInfo) -> ! {
// @todo rect() + drawtext("PANIC")?
endless_sleep()
}
// Kernel entry point
// arch crate is responsible for calling this
pub fn kmain() -> ! {
fn kmain() -> ! {
let mut uart = MiniUart::new();
uart.init();
writeln!(uart, "Hey there, mini uart talking!");
@ -65,9 +58,12 @@ pub fn kmain() -> ! {
}
writeln!(uart, "Bye, going to sleep now");
qemu_aarch64_exit(); //endless_sleep()
// qemu_aarch64_exit()
endless_sleep()
}
entry!(kmain);
// From https://stackoverflow.com/a/49930361/895245
// @todo specify exit value depending on tests result?
fn qemu_aarch64_exit() -> ! {