diff --git a/src/arch/aarch64/mod.rs b/src/arch/aarch64/mod.rs
index 6681edf..8d7b330 100644
--- a/src/arch/aarch64/mod.rs
+++ b/src/arch/aarch64/mod.rs
@@ -7,7 +7,7 @@ pub mod traps;
 pub use self::memory::{PhysicalAddress, VirtualAddress};
 pub use mmu::*;
 
-use cortex_a::{asm, barrier, regs::*};
+use cortex_a::{asm, regs::*};
 
 #[no_mangle]
 static mut WAIT_FLAG: bool = true;
@@ -25,14 +25,6 @@ pub fn jtag_dbg_wait() {
     unsafe { write_volatile(&mut WAIT_FLAG, true) }
 }
 
-// Data memory barrier
-#[inline]
-pub fn dmb() {
-    unsafe {
-        barrier::dmb(barrier::SY);
-    }
-}
-
 #[inline]
 pub fn flushcache(address: usize) {
     unsafe {
diff --git a/src/platform/mailbox.rs b/src/platform/mailbox.rs
index 2a3469a..0d42e44 100644
--- a/src/platform/mailbox.rs
+++ b/src/platform/mailbox.rs
@@ -1,10 +1,10 @@
 use crate::{
-    arch::*,
     platform::{display::Size2d, rpi3::BcmHost},
     println,
 };
 use core::ops::Deref;
 use core::sync::atomic::{compiler_fence, Ordering};
+use cortex_a::barrier;
 use register::mmio::*;
 
 // Public interface to the mailbox.
@@ -207,7 +207,9 @@ fn write(regs: &RegisterBlock, buf_ptr: u32, channel: u32) -> Result<()> {
             return Err(MboxError::Timeout);
         }
     }
-    dmb();
+    unsafe {
+        barrier::dmb(barrier::SY);
+    }
     regs.WRITE
         .set((buf_ptr & !CHANNEL_MASK) | (channel & CHANNEL_MASK));
     Ok(())
@@ -227,9 +229,13 @@ fn read(regs: &RegisterBlock, expected: u32, channel: u32) -> Result<()> {
         /* Read the data
          * Data memory barriers as we've switched peripheral
          */
-        dmb();
+        unsafe {
+            barrier::dmb(barrier::SY);
+        }
         let data: u32 = regs.READ.get();
-        dmb();
+        unsafe {
+            barrier::dmb(barrier::SY);
+        }
 
         // is it a response to our message?
         if ((data & CHANNEL_MASK) == channel) && ((data & !CHANNEL_MASK) == expected) {