Add mmu::init() from Andre Richter's tutorial
* Does not work on real rpi Gpu memory is corrupted with semi-random patterns
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Berkus Decker
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6cf5551efb
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5666fcbec9
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@ -0,0 +1,249 @@
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/*
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* MIT License
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*
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* Copyright (c) 2018-2019 Andre Richter <andre.o.richter@gmail.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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// use super::uart;
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use cortex_a::{barrier, regs::*};
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use register::register_bitfields;
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/// Parse the ID_AA64MMFR0_EL1 register for runtime information about supported
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/// MMU features.
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// pub fn print_features(uart: &uart::Uart) {
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// let mmfr = ID_AA64MMFR0_EL1.extract();
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// if let Some(ID_AA64MMFR0_EL1::TGran4::Value::Supported) =
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// mmfr.read_as_enum(ID_AA64MMFR0_EL1::TGran4)
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// {
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// uart.puts("[i] MMU: 4 KiB granule supported!\n");
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// }
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// if let Some(ID_AA64MMFR0_EL1::PARange::Value::Bits_40) =
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// mmfr.read_as_enum(ID_AA64MMFR0_EL1::PARange)
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// {
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// uart.puts("[i] MMU: Up to 40 Bit physical address range supported!\n");
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// }
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// }
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register_bitfields! {u64,
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// AArch64 Reference Manual page 2150
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STAGE1_DESCRIPTOR [
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/// Execute-never
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XN OFFSET(54) NUMBITS(1) [
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False = 0,
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True = 1
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],
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/// Various address fields, depending on use case
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LVL2_OUTPUT_ADDR_4KiB OFFSET(21) NUMBITS(27) [], // [47:21]
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NEXT_LVL_TABLE_ADDR_4KiB OFFSET(12) NUMBITS(36) [], // [47:12]
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/// Access flag
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AF OFFSET(10) NUMBITS(1) [
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False = 0,
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True = 1
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],
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/// Shareability field
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SH OFFSET(8) NUMBITS(2) [
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OuterShareable = 0b10,
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InnerShareable = 0b11
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],
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/// Access Permissions
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AP OFFSET(6) NUMBITS(2) [
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RW_EL1 = 0b00,
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RW_EL1_EL0 = 0b01,
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RO_EL1 = 0b10,
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RO_EL1_EL0 = 0b11
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],
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/// Memory attributes index into the MAIR_EL1 register
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AttrIndx OFFSET(2) NUMBITS(3) [],
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TYPE OFFSET(1) NUMBITS(1) [
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Block = 0,
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Table = 1
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],
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VALID OFFSET(0) NUMBITS(1) [
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False = 0,
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True = 1
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]
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]
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}
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trait BaseAddr {
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fn base_addr(&self) -> u64;
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}
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impl BaseAddr for [u64; 512] {
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fn base_addr(&self) -> u64 {
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self as *const u64 as u64
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}
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}
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const NUM_ENTRIES_4KIB: usize = 512;
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// We need a wrapper struct here so that we can make use of the align attribute.
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#[repr(C)]
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#[repr(align(4096))]
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struct PageTable {
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entries: [u64; NUM_ENTRIES_4KIB],
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}
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static mut LVL2_TABLE: PageTable = PageTable {
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entries: [0; NUM_ENTRIES_4KIB],
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};
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static mut SINGLE_LVL3_TABLE: PageTable = PageTable {
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entries: [0; NUM_ENTRIES_4KIB],
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};
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/// Set up identity mapped page tables for the first 1 gigabyte of address
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/// space.
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pub unsafe fn init() {
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// First, define the two memory types that we will map. Normal DRAM and
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// device.
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MAIR_EL1.write(
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// Attribute 1
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MAIR_EL1::Attr1_HIGH::Device
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+ MAIR_EL1::Attr1_LOW_DEVICE::Device_nGnRE
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// Attribute 0
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+ MAIR_EL1::Attr0_HIGH::Memory_OuterWriteBack_NonTransient_ReadAlloc_WriteAlloc
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+ MAIR_EL1::Attr0_LOW_MEMORY::InnerWriteBack_NonTransient_ReadAlloc_WriteAlloc,
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);
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// Two descriptive consts for indexing into the correct MAIR_EL1 attributes.
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mod mair {
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pub const NORMAL: u64 = 0;
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pub const DEVICE: u64 = 1;
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}
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// Set up the first LVL2 entry, pointing to a 4KiB table base address.
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let lvl3_base: u64 = SINGLE_LVL3_TABLE.entries.base_addr() >> 12;
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LVL2_TABLE.entries[0] = (STAGE1_DESCRIPTOR::VALID::True
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+ STAGE1_DESCRIPTOR::TYPE::Table
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+ STAGE1_DESCRIPTOR::NEXT_LVL_TABLE_ADDR_4KiB.val(lvl3_base))
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.value;
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// For educational purposes and fun, let the start of the second 2 MiB block
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// point to the 2 MiB aperture which contains the UART's base address.
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// let uart_phys_base: u64 = (uart::UART_PHYS_BASE >> 21).into();
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// LVL2_TABLE.entries[1] = (STAGE1_DESCRIPTOR::VALID::True
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// + STAGE1_DESCRIPTOR::TYPE::Block
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// + STAGE1_DESCRIPTOR::AttrIndx.val(mair::DEVICE)
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// + STAGE1_DESCRIPTOR::AP::RW_EL1
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// + STAGE1_DESCRIPTOR::SH::OuterShareable
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// + STAGE1_DESCRIPTOR::AF::True
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// + STAGE1_DESCRIPTOR::LVL2_OUTPUT_ADDR_4KiB.val(uart_phys_base)
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// + STAGE1_DESCRIPTOR::XN::True)
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// .value;
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// Fill the rest of the LVL2 (2MiB) entries as block
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// descriptors. Differentiate between normal and device mem.
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let mmio_base: u64 = (super::BcmHost::get_peripheral_address() >> 21).into();
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let common = STAGE1_DESCRIPTOR::VALID::True
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+ STAGE1_DESCRIPTOR::TYPE::Block
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+ STAGE1_DESCRIPTOR::AP::RW_EL1
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+ STAGE1_DESCRIPTOR::AF::True
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+ STAGE1_DESCRIPTOR::XN::True;
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// Notice the skip(2)
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for (i, entry) in LVL2_TABLE.entries.iter_mut().enumerate().skip(2) {
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let j: u64 = i as u64;
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let mem_attr = if j >= mmio_base {
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STAGE1_DESCRIPTOR::SH::OuterShareable + STAGE1_DESCRIPTOR::AttrIndx.val(mair::DEVICE)
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} else {
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STAGE1_DESCRIPTOR::SH::InnerShareable + STAGE1_DESCRIPTOR::AttrIndx.val(mair::NORMAL)
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};
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*entry = (common + mem_attr + STAGE1_DESCRIPTOR::LVL2_OUTPUT_ADDR_4KiB.val(j)).value;
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}
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// Finally, fill the single LVL3 table (4 KiB granule). Differentiate
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// between code+RO and RW pages.
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//
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// Using the linker script, we ensure that the RO area is consecutive and 4
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// KiB aligned, and we export the boundaries via symbols.
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extern "C" {
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// The inclusive start of the read-only area, aka the address of the
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// first byte of the area.
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static mut __ro_start: u64;
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// The non-inclusive end of the read-only area, aka the address of the
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// first byte _after_ the RO area.
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static mut __ro_end: u64;
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}
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const PAGESIZE: u64 = 4096;
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let ro_first_page_index: u64 = &__ro_start as *const _ as u64 / PAGESIZE;
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// Notice the subtraction to calculate the last page index of the RO area
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// and not the first page index after the RO area.
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let ro_last_page_index: u64 = (&__ro_end as *const _ as u64 / PAGESIZE) - 1;
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let common = STAGE1_DESCRIPTOR::VALID::True
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+ STAGE1_DESCRIPTOR::TYPE::Table
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+ STAGE1_DESCRIPTOR::AttrIndx.val(mair::NORMAL)
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+ STAGE1_DESCRIPTOR::SH::InnerShareable
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+ STAGE1_DESCRIPTOR::AF::True;
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for (i, entry) in SINGLE_LVL3_TABLE.entries.iter_mut().enumerate() {
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let j: u64 = i as u64;
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let mem_attr = if j < ro_first_page_index || j > ro_last_page_index {
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STAGE1_DESCRIPTOR::AP::RW_EL1 + STAGE1_DESCRIPTOR::XN::True
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} else {
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STAGE1_DESCRIPTOR::AP::RO_EL1 + STAGE1_DESCRIPTOR::XN::False
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};
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*entry = (common + mem_attr + STAGE1_DESCRIPTOR::NEXT_LVL_TABLE_ADDR_4KiB.val(j)).value;
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}
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// Point to the LVL2 table base address in TTBR0.
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TTBR0_EL1.set_baddr(LVL2_TABLE.entries.base_addr());
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// Configure various settings of stage 1 of the EL1 translation regime.
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let ips = ID_AA64MMFR0_EL1.read(ID_AA64MMFR0_EL1::PARange);
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TCR_EL1.write(
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TCR_EL1::TBI0::Ignored
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+ TCR_EL1::IPS.val(ips)
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+ TCR_EL1::TG0::KiB_4 // 4 KiB granule
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+ TCR_EL1::SH0::Inner
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+ TCR_EL1::ORGN0::WriteBack_ReadAlloc_WriteAlloc_Cacheable
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+ TCR_EL1::IRGN0::WriteBack_ReadAlloc_WriteAlloc_Cacheable
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+ TCR_EL1::EPD0::EnableTTBR0Walks
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+ TCR_EL1::T0SZ.val(34), // Start walks at level 2
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);
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// Switch the MMU on.
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//
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// First, force all previous changes to be seen before the MMU is enabled.
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barrier::isb(barrier::SY);
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// Enable the MMU and turn on data and instruction caching.
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SCTLR_EL1.modify(SCTLR_EL1::M::Enable + SCTLR_EL1::C::Cacheable + SCTLR_EL1::I::Cacheable);
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// Force MMU init to complete before next instruction
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barrier::isb(barrier::SY);
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}
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@ -2,6 +2,7 @@
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mod boot;
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mod memory;
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pub mod mmu;
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pub use self::memory::{PhysicalAddress, VirtualAddress};
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use cortex_a::{asm, barrier, regs::*};
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@ -197,7 +198,7 @@ pub struct BcmHost;
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impl BcmHost {
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// As per https://www.raspberrypi.org/documentation/hardware/raspberrypi/peripheral_addresses.md
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/// This returns the ARM-side physical address where peripherals are mapped.
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pub fn get_peripheral_address() -> PhysicalAddress {
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pub const fn get_peripheral_address() -> u32 {
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0x3f00_0000
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}
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@ -51,6 +51,10 @@ fn kmain() -> ! {
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// uart.puts("Hey there, mini uart talking!\n"); // shall this work though?
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// uart.write_str(); // shall this?
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unsafe {
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aarch64::mmu::init();
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}
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if let Some(mut display) = VC::init_fb(Size2d { x: 800, y: 600 } /*, &mut uart*/) {
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display.rect(10, 10, 250, 250, Color::rgb(32, 96, 64));
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display.draw_text(50, 50, "Hello there!", Color::rgb(128, 192, 255));
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@ -19,12 +19,12 @@ pub fn bus2phys(address: u32) -> u32 {
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// @todo use BcmHost::get_peripheral_address() instead
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pub const PERIPHERAL_BASE: u32 = phys2virt(0x3F00_0000); // Base address for all peripherals
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pub struct BcmHost;
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pub struct BcmHost; // One dupe of this is in arch::aarch64 mod NOW!
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impl BcmHost {
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// As per https://www.raspberrypi.org/documentation/hardware/raspberrypi/peripheral_addresses.md
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/// This returns the ARM-side physical address where peripherals are mapped.
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pub fn get_peripheral_address() -> usize {
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pub fn get_peripheral_address() -> u32 {
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0x3f00_0000
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}
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