Clean up addressing

src/arch/aarch64/mmu.rs

@@ -160,7 +160,7 @@ pub unsafe fn init() {
 
     // Fill the rest of the LVL2 (2MiB) entries as block
     // descriptors. Differentiate between normal and device mem.
-    let mmio_base: u64 = (super::BcmHost::get_peripheral_address() >> 21).into();
+    let mmio_base: u64 = (crate::platform::rpi3::BcmHost::get_peripheral_address() >> 21).into();
     let common = STAGE1_DESCRIPTOR::VALID::True
         + STAGE1_DESCRIPTOR::TYPE::Block
         + STAGE1_DESCRIPTOR::AP::RW_EL1

src/platform/gpio.rs

@@ -1,7 +1,7 @@
-use crate::platform::rpi3::PERIPHERAL_BASE;
+use crate::platform::rpi3::BcmHost;
 use register::mmio::*;
 
-const GPIO_BASE: u32 = PERIPHERAL_BASE + 0x20_0000;
+const GPIO_BASE: u32 = BcmHost::get_peripheral_address() + 0x20_0000;
 
 // The offsets for reach register.
 // From https://wiki.osdev.org/Raspberry_Pi_Bare_Bones

src/platform/mailbox.rs

@@ -1,7 +1,7 @@
 use crate::arch::*;
 use crate::platform::{
     display::Size2d,
-    rpi3::{phys2bus, PERIPHERAL_BASE},
+    rpi3::BcmHost,
     // uart::MiniUart,
 };
 use core::ops::Deref;
@@ -17,7 +17,7 @@ pub struct Mailbox {
 }
 
 // Identity mapped first 1Gb by u-boot
-const MAILBOX_BASE: u32 = PERIPHERAL_BASE + 0xb880;
+const MAILBOX_BASE: u32 = BcmHost::get_peripheral_address() + 0xb880;
 /* Lower 4-bits are channel ID */
 const CHANNEL_MASK: u32 = 0xf;
 
@@ -206,7 +206,7 @@ fn write(regs: &RegisterBlock, buf_ptr: u32, channel: u32) -> Result<()> {
     }
     dmb();
     regs.WRITE
-        .set(phys2bus(buf_ptr & !CHANNEL_MASK) | (channel & CHANNEL_MASK));
+        .set((buf_ptr & !CHANNEL_MASK) | (channel & CHANNEL_MASK));
     Ok(())
 }
 
@@ -286,7 +286,7 @@ impl Mailbox {
     }
 
     pub fn read(&self, channel: u32) -> Result<()> {
-        read(self, phys2bus(self.buffer.as_ptr() as u32), channel)?;
+        read(self, self.buffer.as_ptr() as u32, channel)?;
 
         // let mut uart = MiniUart::new();
         // uart.init();

src/platform/rpi3.rs

@@ -1,24 +1,6 @@
 // See BCM2835-ARM-Peripherals.pdf
 // See https://www.raspberrypi.org/forums/viewtopic.php?t=186090 for more details.
 
-// Physical memory is 0x0000_0000 to 0x4000_0000
-const fn phys2virt(address: u32) -> u32 {
-    address // + 0x8000_0000;
-}
-
-// RAM bus address is 0xC000_0000 to 0xFFFF_FFFF
-// Peripheral bus memory is 0x7E00_0000 to 0x7EFF_FFFF
-pub fn phys2bus(address: u32) -> u32 {
-    address.wrapping_add(0xC000_0000) // L2 cache disabled
-}
-
-pub fn bus2phys(address: u32) -> u32 {
-    address.wrapping_sub(0xC000_0000) // L2 cache disabled
-}
-
-// @todo use BcmHost::get_peripheral_address() instead
-pub const PERIPHERAL_BASE: u32 = phys2virt(0x3F00_0000); // Base address for all peripherals
-
 pub struct BcmHost;
 
 impl BcmHost {

src/platform/uart.rs

@@ -1,10 +1,10 @@
 use crate::arch::*;
-use crate::platform::{gpio, rpi3::PERIPHERAL_BASE};
+use crate::platform::{gpio, rpi3::BcmHost};
 use core::{fmt, ops};
 use register::mmio::*;
 
 // The base address for UART.
-const UART0_BASE: u32 = PERIPHERAL_BASE + 0x20_1000;
+const UART0_BASE: u32 = BcmHost::get_peripheral_address() + 0x20_1000;
 
 // The offsets for reach register for the UART.
 const UART0_DR: u32 = UART0_BASE + 0x00;
@@ -27,7 +27,7 @@ const UART0_ITOP: u32 = UART0_BASE + 0x88;
 const UART0_TDR: u32 = UART0_BASE + 0x8C;
 
 // Mini UART
-pub const UART1_BASE: u32 = PERIPHERAL_BASE + 0x21_5000;
+pub const UART1_BASE: u32 = BcmHost::get_peripheral_address() + 0x21_5000;
 
 #[allow(non_snake_case)]
 #[repr(C)]

src/platform/vc.rs

@@ -1,7 +1,6 @@
 use crate::platform::{
     display::{Display, PixelOrder, Size2d, CHARSIZE_X, CHARSIZE_Y},
     mailbox::{self, channel, response::VAL_LEN_FLAG, tag, GpuFb, Mailbox},
-    rpi3::bus2phys,
 };
 // use core::fmt::Write;
 // use platform::uart::MiniUart;
@@ -66,7 +65,7 @@ impl VC {
         // writeln!(uart, "inited fb_info #2");
 
         Some(Display::new(
-            bus2phys(fb_info.pointer),
+            fb_info.pointer,
             fb_info.size,
             fb_info.depth,
             fb_info.pitch,