From 21d0bdec6b7fac99bceb91e381565957e9d3a80a Mon Sep 17 00:00:00 2001
From: Berkus Decker <berkus+github@metta.systems>
Date: Fri, 1 Feb 2019 10:43:44 +0200
Subject: [PATCH] Update rpi3 target config

---
 doc/rpi3_jtag.md    |  2 +-
 doc/rpi3_target.cfg | 48 ++++++++++++++++++++++++++++++++++-----------
 2 files changed, 38 insertions(+), 12 deletions(-)

diff --git a/doc/rpi3_jtag.md b/doc/rpi3_jtag.md
index 5332685..f71e9cc 100644
--- a/doc/rpi3_jtag.md
+++ b/doc/rpi3_jtag.md
@@ -138,7 +138,7 @@ target create $_TARGETNAME arm11 -chain-position $_TARGETNAME
 $_TARGETNAME configure -event gdb-attach { halt }
 ```
 
-[Source #1](https://electronics.stackexchange.com/questions/249008/how-to-use-rpi-2-to-debug-rpi-model-b-via-jtag-with-openocd/419724#419724), [source #2](https://sysprogs.com/tutorials/preparing-raspberry-pi-for-jtag-debugging/), [source #3](http://openocd.org/doc/html/Reset-Configuration.html), [source #4](http://infocenter.arm.com/help/topic/com.arm.doc.faqs/ka3854.html)
+[Source #1](https://electronics.stackexchange.com/questions/249008/how-to-use-rpi-2-to-debug-rpi-model-b-via-jtag-with-openocd/419724#419724), [source #2](https://sysprogs.com/tutorials/preparing-raspberry-pi-for-jtag-debugging/), [source #3](http://openocd.org/doc/html/Reset-Configuration.html), [source #4](http://infocenter.arm.com/help/topic/com.arm.doc.faqs/ka3854.html), [source #5](https://www.raspberrypi.org/forums/viewtopic.php?p=1013802), [source #6 - proper rpi3 ocd config](https://www.suse.com/c/debugging-raspberry-pi-3-with-jtag/)
 
 * @todo Check the expected tap id:
 > If an SoC provides a JTAG debug interface and contains any CoreSight debug components (including any Cortex processor) you should expect to see the standard JTAG IDCODE of a single CoreSight SWJ-DP as one TAP on the JTAG chain.
diff --git a/doc/rpi3_target.cfg b/doc/rpi3_target.cfg
index 3195679..7fd2254 100644
--- a/doc/rpi3_target.cfg
+++ b/doc/rpi3_target.cfg
@@ -1,25 +1,51 @@
-# Broadcom 2835 on Raspberry Pi as JTAG target
+# Broadcom 2837 on Raspberry Pi 3 as JTAG target
+# From https://www.suse.com/c/debugging-raspberry-pi-3-with-jtag/
 
 telnet_port 4444
 gdb_port 5555
 
-adapter_khz 1000
 transport select jtag
 
+# we need to enable srst even though we don't connect it
+reset_config trst_and_srst
+
+adapter_khz 1000
+jtag_ntrst_delay 500
+
 if { [info exists CHIPNAME] } {
-set _CHIPNAME $CHIPNAME
+    set _CHIPNAME $CHIPNAME
 } else {
-set _CHIPNAME rspi
+    set _CHIPNAME rpi3
 }
 
-if { [info exists CPU_TAPID ] } {
-set _CPU_TAPID $CPU_TAPID
+#
+# Main DAP
+#
+if { [info exists DAP_TAPID] } {
+    set _DAP_TAPID $DAP_TAPID
 } else {
-set _CPU_TAPID 0x07b7617F
+    set _DAP_TAPID 0x4ba00477
 }
 
-jtag newtap $_CHIPNAME arm -irlen 5 -expected-id $_CPU_TAPID
+jtag newtap $_CHIPNAME tap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -enable
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap
 
-set _TARGETNAME $_CHIPNAME.arm
-target create $_TARGETNAME arm11 -chain-position $_TARGETNAME
-$_TARGETNAME configure -event gdb-attach { halt }
+set _TARGETNAME $_CHIPNAME.a53
+set _CTINAME $_CHIPNAME.cti
+
+set DBGBASE {0x80010000 0x80012000 0x80014000 0x80016000}
+set CTIBASE {0x80018000 0x80019000 0x8001a000 0x8001b000}
+set _cores 4
+
+for { set _core 0 } { $_core < $_cores } { incr _core } {
+
+    cti create $_CTINAME.$_core -dap $_CHIPNAME.dap -ap-num 0 \
+        -ctibase [lindex $CTIBASE $_core]
+
+    target create $_TARGETNAME.$_core aarch64 \
+        -dap $_CHIPNAME.dap -coreid $_core \
+        -dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core
+
+    $_TARGETNAME.$_core configure -event reset-assert-post "aarch64 dbginit"
+    $_TARGETNAME.$_core configure -event gdb-attach { halt }
+}