From edbe57378ada6416fb9bd2ca5f5e06e47c09b0ad Mon Sep 17 00:00:00 2001 From: ruv Date: Sun, 31 May 2026 06:27:50 -0400 Subject: [PATCH] =?UTF-8?q?fix(signal/cir):=20un-ignore=20end-to-end=20CIR?= =?UTF-8?q?=20pipeline=20test=20=E2=80=94=20ADR-134=20P2=20fully=20resolve?= =?UTF-8?q?d?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The cir_pipeline end-to-end test was gated on the same dominant_tap_ratio floor; the windowed-ratio fix resolves it. All 6 ADR-134 P2 CIR tests (cir_synthetic 5 + cir_pipeline 1) now pass. signal+cir: 472 pass / 0 fail. Co-Authored-By: claude-flow --- v2/crates/wifi-densepose-signal/tests/cir_pipeline.rs | 1 - 1 file changed, 1 deletion(-) diff --git a/v2/crates/wifi-densepose-signal/tests/cir_pipeline.rs b/v2/crates/wifi-densepose-signal/tests/cir_pipeline.rs index d8a017b9..a6f18f0c 100644 --- a/v2/crates/wifi-densepose-signal/tests/cir_pipeline.rs +++ b/v2/crates/wifi-densepose-signal/tests/cir_pipeline.rs @@ -260,7 +260,6 @@ fn should_detect_unsanitized_phase_when_variance_exceeds_threshold() { /// Verifies the full pipeline: generate CSI → sanitize → estimate → dominant tap /// is at or near the expected delay bin. This is the success-path integration test. #[test] -#[ignore = "ADR-134 P2: end-to-end dominant_tap_ratio gated on ISTA hyperparameter tuning."] fn should_produce_clean_estimate_after_correct_pipeline_order() { let cfg = CirConfig::for_bandwidth_mhz(20); let k_active = cfg.delay_bins / 3;