mirror of https://codeberg.org/topola/topola.git
124 lines
4.1 KiB
Plaintext
124 lines
4.1 KiB
Plaintext
(pcb /home/mikolaj/proj/topola/tests/data/0603_breakout/0603_breakout.dsn
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(parser
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(string_quote ")
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(space_in_quoted_tokens on)
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(host_cad "KiCad's Pcbnew")
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(host_version "8.0.1")
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)
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(resolution um 10)
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(unit um)
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(structure
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(layer F.Cu
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(type signal)
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(property
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(index 0)
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)
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)
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(layer B.Cu
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(type signal)
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(property
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(index 1)
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)
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)
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(boundary
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(path pcb 0 143200 -101700 138700 -101700 138700 -98100 143200 -98100
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143200 -101700)
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)
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(via "Via[0-1]_600:300_um")
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(rule
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(width 200)
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(clearance 200)
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(clearance 200 (type default_smd))
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(clearance 50 (type smd_smd))
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)
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)
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(placement
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(component Resistor_SMD:R_0603_1608Metric
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(place R1 142100.000000 -99900.000000 front -90.000000 (PN R))
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)
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(component Connector_PinHeader_1.00mm:PinHeader_1x02_P1.00mm_Vertical
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(place J1 140200.000000 -99400.000000 front 0.000000 (PN Conn_01x02_Męski))
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)
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)
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(library
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(image Resistor_SMD:R_0603_1608Metric
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(outline (path signal 120 -237.258 522.5 237.258 522.5))
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(outline (path signal 120 -237.258 -522.5 237.258 -522.5))
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(outline (path signal 50 -1480 730 1480 730))
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(outline (path signal 50 -1480 -730 -1480 730))
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(outline (path signal 50 1480 730 1480 -730))
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(outline (path signal 50 1480 -730 -1480 -730))
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(outline (path signal 100 -800 412.5 800 412.5))
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(outline (path signal 100 -800 -412.5 -800 412.5))
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(outline (path signal 100 800 412.5 800 -412.5))
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(outline (path signal 100 800 -412.5 -800 -412.5))
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(pin RoundRect[T]Pad_800x950_200.761_um_0.000000_0 1 -825 0)
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(pin RoundRect[T]Pad_800x950_200.761_um_0.000000_0 2 825 0)
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)
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(image Connector_PinHeader_1.00mm:PinHeader_1x02_P1.00mm_Vertical
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(outline (path signal 120 -695 685 0 685))
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(outline (path signal 120 -695 0 -695 685))
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(outline (path signal 120 -695 -685 -695 -1560))
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(outline (path signal 120 -695 -685 -608.276 -685))
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(outline (path signal 120 -695 -1560 -394.493 -1560))
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(outline (path signal 120 394.493 -1560 695 -1560))
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(outline (path signal 120 608.276 -685 695 -685))
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(outline (path signal 120 695 -685 695 -1560))
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(outline (path signal 50 -1150 1000 -1150 -2000))
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(outline (path signal 50 -1150 -2000 1150 -2000))
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(outline (path signal 50 1150 1000 -1150 1000))
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(outline (path signal 50 1150 -2000 1150 1000))
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(outline (path signal 100 -635 182.5 -317.5 500))
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(outline (path signal 100 -635 -1500 -635 182.5))
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(outline (path signal 100 -317.5 500 635 500))
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(outline (path signal 100 635 500 635 -1500))
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(outline (path signal 100 635 -1500 -635 -1500))
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(pin Rect[A]Pad_850x850_um 1 0 0)
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(pin Oval[A]Pad_850x850_um 2 0 -1000)
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)
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(padstack Oval[A]Pad_850x850_um
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(shape (path F.Cu 850 0 0 0 0))
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(shape (path B.Cu 850 0 0 0 0))
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(attach off)
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)
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(padstack RoundRect[T]Pad_800x950_200.761_um_0.000000_0
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(shape (polygon F.Cu 0 -400.761 275 -385.479 351.828 -341.959 416.959 -276.828 460.479
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-199.999 475.76 200 475.761 276.828 460.479 341.959 416.959
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385.479 351.828 400.76 274.999 400.761 -275 385.479 -351.828
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341.959 -416.959 276.828 -460.479 199.999 -475.76 -200 -475.761
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-276.828 -460.479 -341.959 -416.959 -385.479 -351.828 -400.76 -274.999
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-400.761 275))
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(attach off)
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)
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(padstack Rect[A]Pad_850x850_um
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(shape (rect F.Cu -425 -425 425 425))
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(shape (rect B.Cu -425 -425 425 425))
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(attach off)
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)
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(padstack "Via[0-1]_600:300_um"
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(shape (circle F.Cu 600))
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(shape (circle B.Cu 600))
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(attach off)
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)
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)
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(network
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(net GND
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(pins R1-2 J1-2)
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)
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(net "Net-(J1-Pin_1)"
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(pins R1-1 J1-1)
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)
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(class kicad_default "" GND "Net-(J1-Pin_1)"
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(circuit
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(use_via Via[0-1]_600:300_um)
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)
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(rule
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(width 200)
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(clearance 200)
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)
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)
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)
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(wiring
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)
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)
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