(pcb /home/mikolaj/proj/topola/tests/data/0603_breakout/0603_breakout.dsn (parser (string_quote ") (space_in_quoted_tokens on) (host_cad "KiCad's Pcbnew") (host_version "8.0.1") ) (resolution um 10) (unit um) (structure (layer F.Cu (type signal) (property (index 0) ) ) (layer B.Cu (type signal) (property (index 1) ) ) (boundary (path pcb 0 143200 -101700 138700 -101700 138700 -98100 143200 -98100 143200 -101700) ) (via "Via[0-1]_600:300_um") (rule (width 200) (clearance 200) (clearance 200 (type default_smd)) (clearance 50 (type smd_smd)) ) ) (placement (component Resistor_SMD:R_0603_1608Metric (place R1 142100.000000 -99900.000000 front -90.000000 (PN R)) ) (component Connector_PinHeader_1.00mm:PinHeader_1x02_P1.00mm_Vertical (place J1 140200.000000 -99400.000000 front 0.000000 (PN Conn_01x02_Męski)) ) ) (library (image Resistor_SMD:R_0603_1608Metric (outline (path signal 120 -237.258 522.5 237.258 522.5)) (outline (path signal 120 -237.258 -522.5 237.258 -522.5)) (outline (path signal 50 -1480 730 1480 730)) (outline (path signal 50 -1480 -730 -1480 730)) (outline (path signal 50 1480 730 1480 -730)) (outline (path signal 50 1480 -730 -1480 -730)) (outline (path signal 100 -800 412.5 800 412.5)) (outline (path signal 100 -800 -412.5 -800 412.5)) (outline (path signal 100 800 412.5 800 -412.5)) (outline (path signal 100 800 -412.5 -800 -412.5)) (pin RoundRect[T]Pad_800x950_200.761_um_0.000000_0 1 -825 0) (pin RoundRect[T]Pad_800x950_200.761_um_0.000000_0 2 825 0) ) (image Connector_PinHeader_1.00mm:PinHeader_1x02_P1.00mm_Vertical (outline (path signal 120 -695 685 0 685)) (outline (path signal 120 -695 0 -695 685)) (outline (path signal 120 -695 -685 -695 -1560)) (outline (path signal 120 -695 -685 -608.276 -685)) (outline (path signal 120 -695 -1560 -394.493 -1560)) (outline (path signal 120 394.493 -1560 695 -1560)) (outline (path signal 120 608.276 -685 695 -685)) (outline (path signal 120 695 -685 695 -1560)) (outline (path signal 50 -1150 1000 -1150 -2000)) (outline (path signal 50 -1150 -2000 1150 -2000)) (outline (path signal 50 1150 1000 -1150 1000)) (outline (path signal 50 1150 -2000 1150 1000)) (outline (path signal 100 -635 182.5 -317.5 500)) (outline (path signal 100 -635 -1500 -635 182.5)) (outline (path signal 100 -317.5 500 635 500)) (outline (path signal 100 635 500 635 -1500)) (outline (path signal 100 635 -1500 -635 -1500)) (pin Rect[A]Pad_850x850_um 1 0 0) (pin Oval[A]Pad_850x850_um 2 0 -1000) ) (padstack Oval[A]Pad_850x850_um (shape (path F.Cu 850 0 0 0 0)) (shape (path B.Cu 850 0 0 0 0)) (attach off) ) (padstack RoundRect[T]Pad_800x950_200.761_um_0.000000_0 (shape (polygon F.Cu 0 -400.761 275 -385.479 351.828 -341.959 416.959 -276.828 460.479 -199.999 475.76 200 475.761 276.828 460.479 341.959 416.959 385.479 351.828 400.76 274.999 400.761 -275 385.479 -351.828 341.959 -416.959 276.828 -460.479 199.999 -475.76 -200 -475.761 -276.828 -460.479 -341.959 -416.959 -385.479 -351.828 -400.76 -274.999 -400.761 275)) (attach off) ) (padstack Rect[A]Pad_850x850_um (shape (rect F.Cu -425 -425 425 425)) (shape (rect B.Cu -425 -425 425 425)) (attach off) ) (padstack "Via[0-1]_600:300_um" (shape (circle F.Cu 600)) (shape (circle B.Cu 600)) (attach off) ) ) (network (net GND (pins R1-2 J1-2) ) (net "Net-(J1-Pin_1)" (pins R1-1 J1-1) ) (class kicad_default "" GND "Net-(J1-Pin_1)" (circuit (use_via Via[0-1]_600:300_um) ) (rule (width 200) (clearance 200) ) ) ) (wiring ) )