mirror of https://codeberg.org/topola/topola.git
test: Add vga_dac_breakout test
This simple breakout board tests routing around SMD pads.
This commit is contained in:
Mikolaj Wielgus
parent
cc6065099b
commit
ff6d00d34a
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@ -123,7 +123,22 @@ fn test_tht_3pin_xlr_to_tht_3pin_xlr() {
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let (mut autorouter, ..) = invoker.dissolve();
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let (mut autorouter, ..) = invoker.dissolve();
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// FIXME: The routing result is pretty bad.
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common::assert_single_layer_groundless_autoroute(&mut autorouter, "F.Cu");
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}
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#[test]
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fn test_vga_dac_breakout() {
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let mut autorouter =
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common::load_design("tests/single_layer/vga_dac_breakout/vga_dac_breakout.dsn");
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common::assert_navnode_count(&mut autorouter, "J1-2", "R4-1", 944);
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let mut invoker = common::create_invoker_and_assert(autorouter);
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common::replay_and_assert(
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&mut invoker,
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"tests/single_layer/vga_dac_breakout/autoroute_all.cmd",
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);
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let (mut autorouter, ..) = invoker.dissolve();
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common::assert_single_layer_groundless_autoroute(&mut autorouter, "F.Cu");
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common::assert_single_layer_groundless_autoroute(&mut autorouter, "F.Cu");
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}
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}
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@ -0,0 +1,224 @@
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{
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"done": [
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{
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"Autoroute": [
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[
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{
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"pin": "J1-0",
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"layer": "F.Cu"
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},
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{
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"pin": "J1-0@1",
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"layer": "F.Cu"
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},
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{
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"pin": "J1-1",
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"layer": "F.Cu"
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},
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{
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"pin": "J1-10",
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"layer": "F.Cu"
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},
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{
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"pin": "J1-11",
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"layer": "F.Cu"
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},
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{
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"pin": "J1-12",
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"layer": "F.Cu"
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},
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{
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"pin": "J1-13",
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"layer": "F.Cu"
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},
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{
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"pin": "J1-14",
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"layer": "F.Cu"
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},
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{
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"pin": "J1-15",
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"layer": "F.Cu"
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},
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{
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"pin": "J1-2",
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"layer": "F.Cu"
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},
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{
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"pin": "J1-3",
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"layer": "F.Cu"
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},
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{
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"pin": "J1-4",
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"layer": "F.Cu"
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},
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{
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"pin": "J1-5",
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"layer": "F.Cu"
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},
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{
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"pin": "J1-6",
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"layer": "F.Cu"
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},
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{
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"pin": "J1-7",
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"layer": "F.Cu"
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},
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{
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"pin": "J1-8",
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"layer": "F.Cu"
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},
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{
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"pin": "J1-9",
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"layer": "F.Cu"
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},
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{
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"pin": "J2-1",
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"layer": "F.Cu"
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},
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{
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"pin": "J2-2",
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"layer": "F.Cu"
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},
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{
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"pin": "J2-3",
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"layer": "F.Cu"
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},
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{
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"pin": "J2-4",
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"layer": "F.Cu"
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},
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{
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"pin": "J2-5",
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"layer": "F.Cu"
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},
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{
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"pin": "J2-6",
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"layer": "F.Cu"
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},
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{
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"pin": "J3-1",
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"layer": "F.Cu"
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},
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{
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"pin": "J3-2",
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"layer": "F.Cu"
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},
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{
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"pin": "J3-3",
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"layer": "F.Cu"
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},
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{
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"pin": "J3-4",
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"layer": "F.Cu"
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},
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{
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"pin": "J3-5",
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"layer": "F.Cu"
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},
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{
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"pin": "J3-6",
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"layer": "F.Cu"
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},
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{
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"pin": "R1-1",
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"layer": "F.Cu"
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},
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{
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"pin": "R1-2",
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"layer": "F.Cu"
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},
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{
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"pin": "R10-1",
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"layer": "F.Cu"
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},
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{
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"pin": "R10-2",
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"layer": "F.Cu"
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},
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{
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"pin": "R11-1",
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"layer": "F.Cu"
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},
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{
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"pin": "R11-2",
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"layer": "F.Cu"
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},
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{
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"pin": "R2-1",
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"layer": "F.Cu"
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},
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{
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"pin": "R2-2",
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"layer": "F.Cu"
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},
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{
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"pin": "R3-1",
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"layer": "F.Cu"
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},
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{
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"pin": "R3-2",
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"layer": "F.Cu"
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},
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{
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"pin": "R4-1",
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"layer": "F.Cu"
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},
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{
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"pin": "R4-2",
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"layer": "F.Cu"
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},
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{
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"pin": "R5-1",
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"layer": "F.Cu"
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},
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{
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"pin": "R5-2",
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"layer": "F.Cu"
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},
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{
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"pin": "R6-1",
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"layer": "F.Cu"
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},
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{
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"pin": "R6-2",
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"layer": "F.Cu"
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},
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{
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"pin": "R7-1",
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"layer": "F.Cu"
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},
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{
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"pin": "R7-2",
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"layer": "F.Cu"
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},
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{
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"pin": "R8-1",
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"layer": "F.Cu"
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},
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{
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"pin": "R8-2",
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"layer": "F.Cu"
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},
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{
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"pin": "R9-1",
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"layer": "F.Cu"
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},
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{
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"pin": "R9-2",
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"layer": "F.Cu"
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}
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],
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{
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"presort_by": "RatlineIntersectionCountAndLength",
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"permutate": true,
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"router_options": {
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"routed_band_width": 100.0,
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"wrap_around_bands": true,
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"squeeze_through_under_bends": true
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}
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}
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]
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}
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],
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"undone": []
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}
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@ -0,0 +1,697 @@
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(pcb /home/mikolaj/proj/topola/tests/single_layer/vga_dac_breakout/vga_dac_breakout.dsn
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(parser
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(string_quote ")
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(space_in_quoted_tokens on)
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(host_cad "KiCad's Pcbnew")
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(host_version "9.0.2")
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)
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(resolution um 10)
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(unit um)
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(structure
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(layer F.Cu
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(type signal)
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(property
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(index 0)
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)
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)
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(layer B.Cu
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(type signal)
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(property
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(index 1)
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)
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)
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(boundary
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(path pcb 0 166500 -145000 133500 -145000 133500 -103250 166500 -103250
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166500 -145000)
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)
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(via "Via[0-1]_600:300_um")
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(rule
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(width 200)
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(clearance 200)
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(clearance 50 (type smd_smd))
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)
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)
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(placement
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(component Resistor_SMD:R_1206_3216Metric
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(place R9 155962.500000 -115000.000000 front 0.000000 (PN 510))
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(place R11 154962.500000 -121000.000000 front 0.000000 (PN 200))
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(place R8 155962.500000 -112500.000000 front 0.000000 (PN 1K))
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(place R10 155000.000000 -118500.000000 front 0.000000 (PN 200))
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(place R7 155962.500000 -110000.000000 front 0.000000 (PN 2K))
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)
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(component Resistor_SMD:R_1206_3216Metric::1
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(place R1 144000.000000 -123500.000000 front 180.000000 (PN 2K))
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(place R5 143955.000000 -112500.000000 front 180.000000 (PN 1K))
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(place R2 144000.000000 -121000.000000 front 180.000000 (PN 1K))
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(place R6 143917.500000 -110000.000000 front 180.000000 (PN 510))
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(place R4 143955.000000 -115000.000000 front 180.000000 (PN 2K))
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(place R3 144000.000000 -118500.000000 front 180.000000 (PN 510))
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)
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(component TerminalBlock_4Ucon:TerminalBlock_4Ucon_1x06_P3.50mm_Vertical
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(place J2 138250.000000 -108000.000000 back 90.000000 (PN Screw_Terminal_01x06))
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)
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(component "Connector_Dsub:DSUB-15-HD_Socket_Horizontal_P2.29x2.54mm_EdgePinOffset8.35mm_Housed_MountingHolesOffset10.89mm"
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(place J1 145680.000000 -131214.669000 back 0.000000 (PN DE15_Socket_HighDensity_MountingHoles))
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)
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(component TerminalBlock_4Ucon:TerminalBlock_4Ucon_1x06_P3.50mm_Vertical::1
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(place J3 161750.000000 -125500.000000 back 270.000000 (PN Screw_Terminal_01x06))
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)
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)
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(library
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(image Resistor_SMD:R_1206_3216Metric
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(outline (path signal 120 -727.064 910 727.064 910))
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(outline (path signal 120 -727.064 -910 727.064 -910))
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(outline (path signal 50 -2280 1130 2280 1130))
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(outline (path signal 50 -2280 -1130 -2280 1130))
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(outline (path signal 50 2280 1130 2280 -1130))
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(outline (path signal 50 2280 -1130 -2280 -1130))
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(outline (path signal 100 -1600 800 1600 800))
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(outline (path signal 100 -1600 -800 -1600 800))
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(outline (path signal 100 1600 800 1600 -800))
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(outline (path signal 100 1600 -800 -1600 -800))
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(pin RoundRect[T]Pad_1125.000000x1750.000000_250.951000_um_0.000000_0 1 -1462.5 0)
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(pin RoundRect[T]Pad_1125.000000x1750.000000_250.951000_um_0.000000_0 2 1462.5 0)
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)
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(image Resistor_SMD:R_1206_3216Metric::1
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(outline (path signal 120 -727.064 -910 727.064 -910))
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(outline (path signal 120 -727.064 910 727.064 910))
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(outline (path signal 50 2280 -1130 -2280 -1130))
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(outline (path signal 50 2280 1130 2280 -1130))
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(outline (path signal 50 -2280 -1130 -2280 1130))
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(outline (path signal 50 -2280 1130 2280 1130))
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(outline (path signal 100 1600 -800 -1600 -800))
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(outline (path signal 100 1600 800 1600 -800))
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(outline (path signal 100 -1600 -800 -1600 800))
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(outline (path signal 100 -1600 800 1600 800))
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(pin RoundRect[T]Pad_1125.000000x1750.000000_250.951000_um_0.000000_0 1 -1462.5 0)
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(pin RoundRect[T]Pad_1125.000000x1750.000000_250.951000_um_0.000000_0 2 1462.5 0)
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)
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(image TerminalBlock_4Ucon:TerminalBlock_4Ucon_1x06_P3.50mm_Vertical
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(outline (path signal 120 -2370 3820 19870 3820))
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(outline (path signal 120 -2370 3820 -2370 -4720))
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(outline (path signal 120 19870 3820 19870 -4720))
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(outline (path signal 120 -1400 3000 1400 3000))
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(outline (path signal 120 -1400 3000 -1400 1780))
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(outline (path signal 120 1400 3000 1400 1780))
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(outline (path signal 120 2100 3000 4900 3000))
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(outline (path signal 120 2100 3000 2100 1099))
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(outline (path signal 120 4900 3000 4900 1099))
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(outline (path signal 120 5600 3000 8400 3000))
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(outline (path signal 120 5600 3000 5600 1099))
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(outline (path signal 120 9100 3000 11900 3000))
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(outline (path signal 120 11900 3000 11900 1099))
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(outline (path signal 120 12600 3000 15400 3000))
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(outline (path signal 120 15400 3000 15400 1099))
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(outline (path signal 120 16100 3000 18900 3000))
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(outline (path signal 120 16100 3000 16100 1099))
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(outline (path signal 120 18900 3000 18900 1099))
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(outline (path signal 120 -2370 -1100 -1780 -1100))
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(outline (path signal 120 1780 -1100 2101 -1100))
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(outline (path signal 120 4899 -1100 5601 -1100))
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(outline (path signal 120 8399 -1100 9101 -1100))
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(outline (path signal 120 11899 -1100 12601 -1100))
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(outline (path signal 120 15399 -1100 16101 -1100))
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(outline (path signal 120 18899 -1100 19870 -1100))
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(outline (path signal 120 -2370 -4720 -300 -4720))
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(outline (path signal 120 300 -4720 19870 -4720))
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(outline (path signal 0 1039.43 1790.16 1039.43 1757.04 1006.96 1724.57 961.039 1724.57
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928.567 1757.04 928.567 1769.84 924.984 1769.18 873.38 1948.25
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787.478 2113.63 670.65 2258.83 527.484 2378.13 363.603 2466.86
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185.443 2521.53 0 2540 -185.443 2521.53 -363.603 2466.86
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||||||
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||||||
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290.902 2619.32 473.762 2548.28 640.407 2444.78 785.135 2312.35
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||||||
|
4436.79 1672.19 4404.06 1856.2 4335.55 2030.08 4233.99 2186.97
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||||||
|
4103.38 2320.65 3948.89 2425.83 3776.64 2498.35 3593.45 2535.34
|
||||||
|
3406.55 2535.34 3223.36 2498.35 3051.11 2425.83 2896.62 2320.65
|
||||||
|
2766.01 2186.97 2664.45 2030.08 2595.94 1856.2 2563.21 1672.19
|
||||||
|
2567.55 1485.35 2563.43 1484.84 2563.43 1455.04 2530.96 1422.57
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||||||
|
2485.04 1422.57 2452.57 1455.04 2452.57 1471.16 2448.45 1470.65
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||||||
|
2442.73 1669.66 2474.34 1866.22 2542.16 2053.4 2643.8 2224.59
|
||||||
|
2775.67 2373.74 2933.12 2495.6 3110.58 2585.84 3301.79 2641.3
|
||||||
|
3500 2660 3698.21 2641.3 3889.42 2585.84 4066.88 2495.6 4224.33 2373.74
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||||||
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7936.79 1672.19 7904.06 1856.2 7835.55 2030.08 7733.99 2186.97
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||||||
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7603.38 2320.65 7448.89 2425.83 7276.64 2498.35 7093.45 2535.34
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||||||
|
6906.55 2535.34 6723.36 2498.35 6551.11 2425.83 6396.62 2320.65
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||||||
|
6266.01 2186.97 6164.45 2030.08 6095.94 1856.2 6063.21 1672.19
|
||||||
|
6067.55 1485.35 6063.43 1484.84 6063.43 1455.04 6030.96 1422.57
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||||||
|
5985.04 1422.57 5952.57 1455.04 5952.57 1471.16 5948.45 1470.65
|
||||||
|
5942.73 1669.66 5974.34 1866.22 6042.16 2053.4 6143.8 2224.59
|
||||||
|
6275.67 2373.74 6433.12 2495.6 6610.58 2585.84 6801.79 2641.3
|
||||||
|
7000 2660 7198.21 2641.3 7389.42 2585.84 7566.88 2495.6 7724.33 2373.74
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11469 1422.57 11436.6 1455.04 11436.6 1484.84 11432.5 1485.35
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||||||
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11436.8 1672.19 11404.1 1856.2 11335.6 2030.08 11234 2186.97
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||||||
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11103.4 2320.65 10948.9 2425.83 10776.6 2498.35 10593.4 2535.34
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||||||
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10406.6 2535.34 10223.4 2498.35 10051.1 2425.83 9896.62 2320.65
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||||||
|
9766.01 2186.97 9664.45 2030.08 9595.94 1856.2 9563.21 1672.19
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||||||
|
9567.55 1485.35 9563.43 1484.84 9563.43 1455.04 9530.96 1422.57
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||||||
|
9485.04 1422.57 9452.57 1455.04 9452.57 1471.16 9448.45 1470.65
|
||||||
|
9442.73 1669.66 9474.34 1866.22 9542.16 2053.4 9643.8 2224.59
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||||||
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9775.67 2373.74 9933.12 2495.6 10110.6 2585.84 10301.8 2641.3
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||||||
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10500 2660 10698.2 2641.3 10889.4 2585.84 11066.9 2495.6
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||||||
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11224.3 2373.74 11356.2 2224.59 11457.8 2053.4 11525.7 1866.22
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14936.8 1672.19 14904.1 1856.2 14835.6 2030.08 14734 2186.97
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14603.4 2320.65 14448.9 2425.83 14276.6 2498.35 14093.4 2535.34
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||||||
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||||||
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13266 2186.97 13164.4 2030.08 13095.9 1856.2 13063.2 1672.19
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||||||
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13067.5 1485.35 13063.4 1484.84 13063.4 1455.04 13031 1422.57
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||||||
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12985 1422.57 12952.6 1455.04 12952.6 1471.16 12948.5 1470.65
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||||||
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12942.7 1669.66 12974.3 1866.22 13042.2 2053.4 13143.8 2224.59
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||||||
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13275.7 2373.74 13433.1 2495.6 13610.6 2585.84 13801.8 2641.3
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14000 2660 14198.2 2641.3 14389.4 2585.84 14566.9 2495.6
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||||||
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14724.3 2373.74 14856.2 2224.59 14957.8 2053.4 15025.7 1866.22
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||||||
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16766 2186.97 16664.4 2030.08 16595.9 1856.2 16563.2 1672.19
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||||||
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16567.5 1485.35 16563.4 1484.84 16563.4 1455.04 16531 1422.57
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||||||
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||||||
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||||||
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17500 2660 17698.2 2641.3 17889.4 2585.84 18066.9 2495.6
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||||||
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18224.3 2373.74 18356.2 2224.59 18457.8 2053.4 18525.7 1866.22
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0 2600 195.09 2580.78 382.683 2523.88 555.57 2431.47 707.107 2307.11
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||||||
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831.47 2155.57 923.88 1982.68 980.785 1795.09 1000 1600 980.785 1404.91
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||||||
|
923.88 1217.32 831.47 1044.43 707.107 892.893 555.57 768.53
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||||||
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2500 1600 2519.22 1795.09 2576.12 1982.68 2668.53 2155.57
|
||||||
|
2792.89 2307.11 2944.43 2431.47 3117.32 2523.88 3304.91 2580.78
|
||||||
|
3500 2600 3695.09 2580.78 3882.68 2523.88 4055.57 2431.47
|
||||||
|
4207.11 2307.11 4331.47 2155.57 4423.88 1982.68 4480.78 1795.09
|
||||||
|
4500 1600 4480.78 1404.91 4423.88 1217.32 4331.47 1044.43
|
||||||
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4207.11 892.893 4055.57 768.53 3882.68 676.12 3695.09 619.215
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||||||
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6000 1600 6019.22 1795.09 6076.12 1982.68 6168.53 2155.57
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||||||
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6292.89 2307.11 6444.43 2431.47 6617.32 2523.88 6804.91 2580.78
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||||||
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7000 2600 7195.09 2580.78 7382.68 2523.88 7555.57 2431.47
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||||||
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7707.11 2307.11 7831.47 2155.57 7923.88 1982.68 7980.78 1795.09
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||||||
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8000 1600 7980.78 1404.91 7923.88 1217.32 7831.47 1044.43
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||||||
|
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||||||
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9500 1600 9519.22 1795.09 9576.12 1982.68 9668.53 2155.57
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10500 2600 10695.1 2580.78 10882.7 2523.88 11055.6 2431.47
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11207.1 2307.11 11331.5 2155.57 11423.9 1982.68 11480.8 1795.09
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||||||
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11500 1600 11480.8 1404.91 11423.9 1217.32 11331.5 1044.43
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||||||
|
2944.43 2431.47 3117.32 2523.88 3304.91 2580.78 3500 2600))
|
||||||
|
(outline (path signal 100 0 2600 195.09 2580.78 382.683 2523.88 555.57 2431.47
|
||||||
|
707.107 2307.11 831.47 2155.57 923.88 1982.68 980.785 1795.09
|
||||||
|
1000 1600 980.785 1404.91 923.88 1217.32 831.47 1044.43 707.107 892.893
|
||||||
|
555.57 768.53 382.683 676.12 195.09 619.215 0 600 -195.09 619.215
|
||||||
|
-382.683 676.12 -555.57 768.53 -707.107 892.893 -831.47 1044.43
|
||||||
|
-923.88 1217.32 -980.785 1404.91 -1000 1600 -980.785 1795.09
|
||||||
|
-923.88 1982.68 -831.47 2155.57 -707.107 2307.11 -555.57 2431.47
|
||||||
|
-382.683 2523.88 -195.09 2580.78 0 2600))
|
||||||
|
(pin RoundRect[A]Pad_2600.000000x2600.000000_250.951000_um_0.000000_0 1 0 0)
|
||||||
|
(pin Round[A]Pad_2600.000000_um 2 3500 0)
|
||||||
|
(pin Round[A]Pad_2600.000000_um 3 7000 0)
|
||||||
|
(pin Round[A]Pad_2600.000000_um 4 10500 0)
|
||||||
|
(pin Round[A]Pad_2600.000000_um 5 14000 0)
|
||||||
|
(pin Round[A]Pad_2600.000000_um 6 17500 0)
|
||||||
|
)
|
||||||
|
(padstack Round[A]Pad_1600.000000_um
|
||||||
|
(shape (circle F.Cu 1600))
|
||||||
|
(shape (circle B.Cu 1600))
|
||||||
|
(attach off)
|
||||||
|
)
|
||||||
|
(padstack Round[A]Pad_2600.000000_um
|
||||||
|
(shape (circle F.Cu 2600))
|
||||||
|
(shape (circle B.Cu 2600))
|
||||||
|
(attach off)
|
||||||
|
)
|
||||||
|
(padstack Round[A]Pad_4000.000000_um
|
||||||
|
(shape (circle F.Cu 4000))
|
||||||
|
(shape (circle B.Cu 4000))
|
||||||
|
(attach off)
|
||||||
|
)
|
||||||
|
(padstack RoundRect[A]Pad_2600.000000x2600.000000_250.951000_um_0.000000_0
|
||||||
|
(shape (polygon F.Cu 0 -1300.95 1050 -1281.85 1146.04 -1227.45 1227.45 -1146.04 1281.85
|
||||||
|
-1050 1300.95 1050 1300.95 1146.04 1281.85 1227.45 1227.45
|
||||||
|
1281.85 1146.04 1300.95 1050 1300.95 -1050 1281.85 -1146.04
|
||||||
|
1227.45 -1227.45 1146.04 -1281.85 1050 -1300.95 -1050 -1300.95
|
||||||
|
-1146.04 -1281.85 -1227.45 -1227.45 -1281.85 -1146.04 -1300.95 -1050
|
||||||
|
-1300.95 1050))
|
||||||
|
(shape (polygon B.Cu 0 -1300.95 1050 -1281.85 1146.04 -1227.45 1227.45 -1146.04 1281.85
|
||||||
|
-1050 1300.95 1050 1300.95 1146.04 1281.85 1227.45 1227.45
|
||||||
|
1281.85 1146.04 1300.95 1050 1300.95 -1050 1281.85 -1146.04
|
||||||
|
1227.45 -1227.45 1146.04 -1281.85 1050 -1300.95 -1050 -1300.95
|
||||||
|
-1146.04 -1281.85 -1227.45 -1227.45 -1281.85 -1146.04 -1300.95 -1050
|
||||||
|
-1300.95 1050))
|
||||||
|
(attach off)
|
||||||
|
)
|
||||||
|
(padstack RoundRect[T]Pad_1125.000000x1750.000000_250.951000_um_0.000000_0
|
||||||
|
(shape (polygon F.Cu 0 -563.451 625 -544.348 721.035 -489.949 802.449 -408.535 856.848
|
||||||
|
-312.499 875.95 312.5 875.951 408.535 856.848 489.949 802.449
|
||||||
|
544.348 721.035 563.45 624.999 563.451 -625 544.348 -721.035
|
||||||
|
489.949 -802.449 408.535 -856.848 312.499 -875.95 -312.5 -875.951
|
||||||
|
-408.535 -856.848 -489.949 -802.449 -544.348 -721.035 -563.45 -624.999
|
||||||
|
-563.451 625))
|
||||||
|
(attach off)
|
||||||
|
)
|
||||||
|
(padstack Rect[A]Pad_1600.000000x1600.000000_um
|
||||||
|
(shape (rect F.Cu -800 -800 800 800))
|
||||||
|
(shape (rect B.Cu -800 -800 800 800))
|
||||||
|
(attach off)
|
||||||
|
)
|
||||||
|
(padstack "Via[0-1]_600:300_um"
|
||||||
|
(shape (circle F.Cu 600))
|
||||||
|
(shape (circle B.Cu 600))
|
||||||
|
(attach off)
|
||||||
|
)
|
||||||
|
)
|
||||||
|
(network
|
||||||
|
(net "unconnected-(J1-Pad4)"
|
||||||
|
(pins J1-4)
|
||||||
|
)
|
||||||
|
(net "Net-(J3-Pin_1)"
|
||||||
|
(pins J1-0 J1-0@1 J1-5 J1-6 J1-7 J1-8 J1-10 J3-1)
|
||||||
|
)
|
||||||
|
(net "unconnected-(J1-Pad11)"
|
||||||
|
(pins J1-11)
|
||||||
|
)
|
||||||
|
(net "unconnected-(J1-Pad9)"
|
||||||
|
(pins J1-9)
|
||||||
|
)
|
||||||
|
(net "unconnected-(J1-Pad12)"
|
||||||
|
(pins J1-12)
|
||||||
|
)
|
||||||
|
(net "unconnected-(J1-Pad15)"
|
||||||
|
(pins J1-15)
|
||||||
|
)
|
||||||
|
(net "Net-(J1-Pad2)"
|
||||||
|
(pins R5-1 R6-1 R4-1 J1-2)
|
||||||
|
)
|
||||||
|
(net "Net-(J1-Pad3)"
|
||||||
|
(pins R9-1 R8-1 R7-1 J1-3)
|
||||||
|
)
|
||||||
|
(net "Net-(J1-Pad1)"
|
||||||
|
(pins R1-1 R2-1 R3-1 J1-1)
|
||||||
|
)
|
||||||
|
(net "Net-(J2-Pin_1)"
|
||||||
|
(pins R6-2 J2-1)
|
||||||
|
)
|
||||||
|
(net "Net-(J2-Pin_2)"
|
||||||
|
(pins R5-2 J2-2)
|
||||||
|
)
|
||||||
|
(net "Net-(J2-Pin_3)"
|
||||||
|
(pins R4-2 J2-3)
|
||||||
|
)
|
||||||
|
(net "Net-(J2-Pin_4)"
|
||||||
|
(pins R3-2 J2-4)
|
||||||
|
)
|
||||||
|
(net "Net-(J2-Pin_5)"
|
||||||
|
(pins R2-2 J2-5)
|
||||||
|
)
|
||||||
|
(net "Net-(J2-Pin_6)"
|
||||||
|
(pins R1-2 J2-6)
|
||||||
|
)
|
||||||
|
(net "Net-(J1-Pad13)"
|
||||||
|
(pins R10-1 J1-13)
|
||||||
|
)
|
||||||
|
(net "Net-(J1-Pad14)"
|
||||||
|
(pins R11-1 J1-14)
|
||||||
|
)
|
||||||
|
(net "Net-(J3-Pin_6)"
|
||||||
|
(pins R7-2 J3-6)
|
||||||
|
)
|
||||||
|
(net "Net-(J3-Pin_5)"
|
||||||
|
(pins R8-2 J3-5)
|
||||||
|
)
|
||||||
|
(net "Net-(J3-Pin_4)"
|
||||||
|
(pins R9-2 J3-4)
|
||||||
|
)
|
||||||
|
(net "Net-(J3-Pin_3)"
|
||||||
|
(pins R10-2 J3-3)
|
||||||
|
)
|
||||||
|
(net "Net-(J3-Pin_2)"
|
||||||
|
(pins R11-2 J3-2)
|
||||||
|
)
|
||||||
|
(class kicad_default "Net-(J1-Pad1)" "Net-(J1-Pad13)" "Net-(J1-Pad14)"
|
||||||
|
"Net-(J1-Pad2)" "Net-(J1-Pad3)" "Net-(J2-Pin_1)" "Net-(J2-Pin_2)" "Net-(J2-Pin_3)"
|
||||||
|
"Net-(J2-Pin_4)" "Net-(J2-Pin_5)" "Net-(J2-Pin_6)" "Net-(J3-Pin_1)"
|
||||||
|
"Net-(J3-Pin_2)" "Net-(J3-Pin_3)" "Net-(J3-Pin_4)" "Net-(J3-Pin_5)"
|
||||||
|
"Net-(J3-Pin_6)" "unconnected-(J1-Pad11)" "unconnected-(J1-Pad12)" "unconnected-(J1-Pad15)"
|
||||||
|
"unconnected-(J1-Pad4)" "unconnected-(J1-Pad9)"
|
||||||
|
(circuit
|
||||||
|
(use_via "Via[0-1]_600:300_um")
|
||||||
|
)
|
||||||
|
(rule
|
||||||
|
(width 200)
|
||||||
|
(clearance 200)
|
||||||
|
)
|
||||||
|
)
|
||||||
|
)
|
||||||
|
(wiring
|
||||||
|
)
|
||||||
|
)
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,130 @@
|
||||||
|
{
|
||||||
|
"board": {
|
||||||
|
"active_layer": 0,
|
||||||
|
"active_layer_preset": "All Layers",
|
||||||
|
"auto_track_width": true,
|
||||||
|
"hidden_netclasses": [],
|
||||||
|
"hidden_nets": [],
|
||||||
|
"high_contrast_mode": 0,
|
||||||
|
"net_color_mode": 1,
|
||||||
|
"opacity": {
|
||||||
|
"images": 0.6,
|
||||||
|
"pads": 1.0,
|
||||||
|
"shapes": 1.0,
|
||||||
|
"tracks": 1.0,
|
||||||
|
"vias": 1.0,
|
||||||
|
"zones": 0.6
|
||||||
|
},
|
||||||
|
"selection_filter": {
|
||||||
|
"dimensions": true,
|
||||||
|
"footprints": true,
|
||||||
|
"graphics": true,
|
||||||
|
"keepouts": true,
|
||||||
|
"lockedItems": false,
|
||||||
|
"otherItems": true,
|
||||||
|
"pads": true,
|
||||||
|
"text": true,
|
||||||
|
"tracks": true,
|
||||||
|
"vias": true,
|
||||||
|
"zones": true
|
||||||
|
},
|
||||||
|
"visible_items": [
|
||||||
|
"vias",
|
||||||
|
"footprint_text",
|
||||||
|
"footprint_anchors",
|
||||||
|
"ratsnest",
|
||||||
|
"grid",
|
||||||
|
"footprints_front",
|
||||||
|
"footprints_back",
|
||||||
|
"footprint_values",
|
||||||
|
"footprint_references",
|
||||||
|
"tracks",
|
||||||
|
"drc_errors",
|
||||||
|
"drawing_sheet",
|
||||||
|
"bitmaps",
|
||||||
|
"pads",
|
||||||
|
"zones",
|
||||||
|
"drc_warnings",
|
||||||
|
"locked_item_shadows",
|
||||||
|
"conflict_shadows",
|
||||||
|
"shapes"
|
||||||
|
],
|
||||||
|
"visible_layers": "ffffffff_ffffffff_ffffffff_ffffffff",
|
||||||
|
"zone_display_mode": 0
|
||||||
|
},
|
||||||
|
"git": {
|
||||||
|
"repo_type": "",
|
||||||
|
"repo_username": "",
|
||||||
|
"ssh_key": ""
|
||||||
|
},
|
||||||
|
"meta": {
|
||||||
|
"filename": "vga_dac_breakout.kicad_prl",
|
||||||
|
"version": 5
|
||||||
|
},
|
||||||
|
"net_inspector_panel": {
|
||||||
|
"col_hidden": [
|
||||||
|
false,
|
||||||
|
false,
|
||||||
|
false,
|
||||||
|
false,
|
||||||
|
false,
|
||||||
|
false,
|
||||||
|
false,
|
||||||
|
false,
|
||||||
|
false,
|
||||||
|
false
|
||||||
|
],
|
||||||
|
"col_order": [
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
2,
|
||||||
|
3,
|
||||||
|
4,
|
||||||
|
5,
|
||||||
|
6,
|
||||||
|
7,
|
||||||
|
8,
|
||||||
|
9
|
||||||
|
],
|
||||||
|
"col_widths": [
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0
|
||||||
|
],
|
||||||
|
"custom_group_rules": [],
|
||||||
|
"expanded_rows": [],
|
||||||
|
"filter_by_net_name": true,
|
||||||
|
"filter_by_netclass": true,
|
||||||
|
"filter_text": "",
|
||||||
|
"group_by_constraint": false,
|
||||||
|
"group_by_netclass": false,
|
||||||
|
"show_unconnected_nets": false,
|
||||||
|
"show_zero_pad_nets": false,
|
||||||
|
"sort_ascending": true,
|
||||||
|
"sorting_column": 0
|
||||||
|
},
|
||||||
|
"open_jobsets": [],
|
||||||
|
"project": {
|
||||||
|
"files": []
|
||||||
|
},
|
||||||
|
"schematic": {
|
||||||
|
"selection_filter": {
|
||||||
|
"graphics": true,
|
||||||
|
"images": true,
|
||||||
|
"labels": true,
|
||||||
|
"lockedItems": false,
|
||||||
|
"otherItems": true,
|
||||||
|
"pins": true,
|
||||||
|
"symbols": true,
|
||||||
|
"text": true,
|
||||||
|
"wires": true
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,618 @@
|
||||||
|
{
|
||||||
|
"board": {
|
||||||
|
"3dviewports": [],
|
||||||
|
"design_settings": {
|
||||||
|
"defaults": {
|
||||||
|
"apply_defaults_to_fp_fields": false,
|
||||||
|
"apply_defaults_to_fp_shapes": false,
|
||||||
|
"apply_defaults_to_fp_text": false,
|
||||||
|
"board_outline_line_width": 0.05,
|
||||||
|
"copper_line_width": 0.2,
|
||||||
|
"copper_text_italic": false,
|
||||||
|
"copper_text_size_h": 1.5,
|
||||||
|
"copper_text_size_v": 1.5,
|
||||||
|
"copper_text_thickness": 0.3,
|
||||||
|
"copper_text_upright": false,
|
||||||
|
"courtyard_line_width": 0.05,
|
||||||
|
"dimension_precision": 4,
|
||||||
|
"dimension_units": 3,
|
||||||
|
"dimensions": {
|
||||||
|
"arrow_length": 1270000,
|
||||||
|
"extension_offset": 500000,
|
||||||
|
"keep_text_aligned": true,
|
||||||
|
"suppress_zeroes": true,
|
||||||
|
"text_position": 0,
|
||||||
|
"units_format": 0
|
||||||
|
},
|
||||||
|
"fab_line_width": 0.1,
|
||||||
|
"fab_text_italic": false,
|
||||||
|
"fab_text_size_h": 1.0,
|
||||||
|
"fab_text_size_v": 1.0,
|
||||||
|
"fab_text_thickness": 0.15,
|
||||||
|
"fab_text_upright": false,
|
||||||
|
"other_line_width": 0.1,
|
||||||
|
"other_text_italic": false,
|
||||||
|
"other_text_size_h": 1.0,
|
||||||
|
"other_text_size_v": 1.0,
|
||||||
|
"other_text_thickness": 0.15,
|
||||||
|
"other_text_upright": false,
|
||||||
|
"pads": {
|
||||||
|
"drill": 0.8,
|
||||||
|
"height": 1.27,
|
||||||
|
"width": 2.54
|
||||||
|
},
|
||||||
|
"silk_line_width": 0.1,
|
||||||
|
"silk_text_italic": false,
|
||||||
|
"silk_text_size_h": 1.0,
|
||||||
|
"silk_text_size_v": 1.0,
|
||||||
|
"silk_text_thickness": 0.1,
|
||||||
|
"silk_text_upright": false,
|
||||||
|
"zones": {
|
||||||
|
"min_clearance": 0.5
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"diff_pair_dimensions": [],
|
||||||
|
"drc_exclusions": [],
|
||||||
|
"meta": {
|
||||||
|
"version": 2
|
||||||
|
},
|
||||||
|
"rule_severities": {
|
||||||
|
"annular_width": "error",
|
||||||
|
"clearance": "error",
|
||||||
|
"connection_width": "warning",
|
||||||
|
"copper_edge_clearance": "error",
|
||||||
|
"copper_sliver": "warning",
|
||||||
|
"courtyards_overlap": "error",
|
||||||
|
"creepage": "error",
|
||||||
|
"diff_pair_gap_out_of_range": "error",
|
||||||
|
"diff_pair_uncoupled_length_too_long": "error",
|
||||||
|
"drill_out_of_range": "error",
|
||||||
|
"duplicate_footprints": "warning",
|
||||||
|
"extra_footprint": "warning",
|
||||||
|
"footprint": "error",
|
||||||
|
"footprint_filters_mismatch": "ignore",
|
||||||
|
"footprint_symbol_mismatch": "warning",
|
||||||
|
"footprint_type_mismatch": "ignore",
|
||||||
|
"hole_clearance": "error",
|
||||||
|
"hole_to_hole": "warning",
|
||||||
|
"holes_co_located": "warning",
|
||||||
|
"invalid_outline": "error",
|
||||||
|
"isolated_copper": "warning",
|
||||||
|
"item_on_disabled_layer": "error",
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
"mirrored_text_on_front_layer": "warning",
|
||||||
|
"missing_courtyard": "ignore",
|
||||||
|
"missing_footprint": "warning",
|
||||||
|
"net_conflict": "warning",
|
||||||
|
"nonmirrored_text_on_back_layer": "warning",
|
||||||
|
"npth_inside_courtyard": "ignore",
|
||||||
|
"padstack": "warning",
|
||||||
|
"pth_inside_courtyard": "ignore",
|
||||||
|
"shorting_items": "error",
|
||||||
|
"silk_edge_clearance": "warning",
|
||||||
|
"silk_over_copper": "warning",
|
||||||
|
"silk_overlap": "warning",
|
||||||
|
"skew_out_of_range": "error",
|
||||||
|
"solder_mask_bridge": "error",
|
||||||
|
"starved_thermal": "error",
|
||||||
|
"text_height": "warning",
|
||||||
|
"text_on_edge_cuts": "error",
|
||||||
|
"text_thickness": "warning",
|
||||||
|
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|
||||||
|
"too_many_vias": "error",
|
||||||
|
"track_angle": "error",
|
||||||
|
"track_dangling": "warning",
|
||||||
|
"track_segment_length": "error",
|
||||||
|
"track_width": "error",
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
},
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
},
|
||||||
|
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|
||||||
|
{
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
}
|
||||||
|
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|
||||||
|
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|
||||||
|
{
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
{
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
},
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
"spacing": 0.6
|
||||||
|
},
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
}
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
},
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
"mfg": "",
|
||||||
|
"mpn": ""
|
||||||
|
},
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
},
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
},
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
"bus_to_net_conflict": "error",
|
||||||
|
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|
||||||
|
"different_unit_net": "error",
|
||||||
|
"duplicate_reference": "error",
|
||||||
|
"duplicate_sheet_names": "error",
|
||||||
|
"endpoint_off_grid": "warning",
|
||||||
|
"extra_units": "error",
|
||||||
|
"footprint_filter": "ignore",
|
||||||
|
"footprint_link_issues": "warning",
|
||||||
|
"four_way_junction": "ignore",
|
||||||
|
"global_label_dangling": "warning",
|
||||||
|
"hier_label_mismatch": "error",
|
||||||
|
"label_dangling": "error",
|
||||||
|
"label_multiple_wires": "warning",
|
||||||
|
"lib_symbol_issues": "warning",
|
||||||
|
"lib_symbol_mismatch": "warning",
|
||||||
|
"missing_bidi_pin": "warning",
|
||||||
|
"missing_input_pin": "warning",
|
||||||
|
"missing_power_pin": "error",
|
||||||
|
"missing_unit": "warning",
|
||||||
|
"multiple_net_names": "warning",
|
||||||
|
"net_not_bus_member": "warning",
|
||||||
|
"no_connect_connected": "warning",
|
||||||
|
"no_connect_dangling": "warning",
|
||||||
|
"pin_not_connected": "error",
|
||||||
|
"pin_not_driven": "error",
|
||||||
|
"pin_to_pin": "warning",
|
||||||
|
"power_pin_not_driven": "error",
|
||||||
|
"same_local_global_label": "warning",
|
||||||
|
"similar_label_and_power": "warning",
|
||||||
|
"similar_labels": "warning",
|
||||||
|
"similar_power": "warning",
|
||||||
|
"simulation_model_issue": "ignore",
|
||||||
|
"single_global_label": "ignore",
|
||||||
|
"unannotated": "error",
|
||||||
|
"unconnected_wire_endpoint": "warning",
|
||||||
|
"unit_value_mismatch": "error",
|
||||||
|
"unresolved_variable": "error",
|
||||||
|
"wire_dangling": "error"
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"libraries": {
|
||||||
|
"pinned_footprint_libs": [],
|
||||||
|
"pinned_symbol_libs": []
|
||||||
|
},
|
||||||
|
"meta": {
|
||||||
|
"filename": "vga_dac_breakout.kicad_pro",
|
||||||
|
"version": 3
|
||||||
|
},
|
||||||
|
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|
||||||
|
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|
||||||
|
{
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
"name": "Default",
|
||||||
|
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"priority": 2147483647,
|
||||||
|
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|
||||||
|
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|
||||||
|
"via_diameter": 0.6,
|
||||||
|
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|
||||||
|
"wire_width": 6
|
||||||
|
}
|
||||||
|
],
|
||||||
|
"meta": {
|
||||||
|
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|
||||||
|
},
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
},
|
||||||
|
"pcbnew": {
|
||||||
|
"last_paths": {
|
||||||
|
"gencad": "",
|
||||||
|
"idf": "",
|
||||||
|
"netlist": "",
|
||||||
|
"plot": "",
|
||||||
|
"pos_files": "",
|
||||||
|
"specctra_dsn": "vga_dac_breakout.dsn",
|
||||||
|
"step": "",
|
||||||
|
"svg": "",
|
||||||
|
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|
||||||
|
},
|
||||||
|
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|
||||||
|
},
|
||||||
|
"schematic": {
|
||||||
|
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|
||||||
|
"bom_export_filename": "${PROJECTNAME}.csv",
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
"name": "CSV",
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
},
|
||||||
|
"bom_presets": [],
|
||||||
|
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|
||||||
|
"exclude_dnp": false,
|
||||||
|
"fields_ordered": [
|
||||||
|
{
|
||||||
|
"group_by": false,
|
||||||
|
"label": "Reference",
|
||||||
|
"name": "Reference",
|
||||||
|
"show": true
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"group_by": false,
|
||||||
|
"label": "Qty",
|
||||||
|
"name": "${QUANTITY}",
|
||||||
|
"show": true
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"group_by": true,
|
||||||
|
"label": "Value",
|
||||||
|
"name": "Value",
|
||||||
|
"show": true
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"group_by": true,
|
||||||
|
"label": "DNP",
|
||||||
|
"name": "${DNP}",
|
||||||
|
"show": true
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"group_by": true,
|
||||||
|
"label": "Exclude from BOM",
|
||||||
|
"name": "${EXCLUDE_FROM_BOM}",
|
||||||
|
"show": true
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"group_by": true,
|
||||||
|
"label": "Exclude from Board",
|
||||||
|
"name": "${EXCLUDE_FROM_BOARD}",
|
||||||
|
"show": true
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"group_by": true,
|
||||||
|
"label": "Footprint",
|
||||||
|
"name": "Footprint",
|
||||||
|
"show": true
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"group_by": false,
|
||||||
|
"label": "Datasheet",
|
||||||
|
"name": "Datasheet",
|
||||||
|
"show": true
|
||||||
|
}
|
||||||
|
],
|
||||||
|
"filter_string": "",
|
||||||
|
"group_symbols": true,
|
||||||
|
"include_excluded_from_bom": true,
|
||||||
|
"name": "Default Editing",
|
||||||
|
"sort_asc": true,
|
||||||
|
"sort_field": "Reference"
|
||||||
|
},
|
||||||
|
"connection_grid_size": 50.0,
|
||||||
|
"drawing": {
|
||||||
|
"dashed_lines_dash_length_ratio": 12.0,
|
||||||
|
"dashed_lines_gap_length_ratio": 3.0,
|
||||||
|
"default_line_thickness": 6.0,
|
||||||
|
"default_text_size": 50.0,
|
||||||
|
"field_names": [],
|
||||||
|
"intersheets_ref_own_page": false,
|
||||||
|
"intersheets_ref_prefix": "",
|
||||||
|
"intersheets_ref_short": false,
|
||||||
|
"intersheets_ref_show": false,
|
||||||
|
"intersheets_ref_suffix": "",
|
||||||
|
"junction_size_choice": 3,
|
||||||
|
"label_size_ratio": 0.375,
|
||||||
|
"operating_point_overlay_i_precision": 3,
|
||||||
|
"operating_point_overlay_i_range": "~A",
|
||||||
|
"operating_point_overlay_v_precision": 3,
|
||||||
|
"operating_point_overlay_v_range": "~V",
|
||||||
|
"overbar_offset_ratio": 1.23,
|
||||||
|
"pin_symbol_size": 25.0,
|
||||||
|
"text_offset_ratio": 0.15
|
||||||
|
},
|
||||||
|
"legacy_lib_dir": "",
|
||||||
|
"legacy_lib_list": [],
|
||||||
|
"meta": {
|
||||||
|
"version": 1
|
||||||
|
},
|
||||||
|
"net_format_name": "",
|
||||||
|
"page_layout_descr_file": "",
|
||||||
|
"plot_directory": "",
|
||||||
|
"space_save_all_events": true,
|
||||||
|
"spice_current_sheet_as_root": false,
|
||||||
|
"spice_external_command": "spice \"%I\"",
|
||||||
|
"spice_model_current_sheet_as_root": true,
|
||||||
|
"spice_save_all_currents": false,
|
||||||
|
"spice_save_all_dissipations": false,
|
||||||
|
"spice_save_all_voltages": false,
|
||||||
|
"subpart_first_id": 65,
|
||||||
|
"subpart_id_separator": 0
|
||||||
|
},
|
||||||
|
"sheets": [
|
||||||
|
[
|
||||||
|
"6653d8db-6e68-4624-904b-f630210886bb",
|
||||||
|
"Root"
|
||||||
|
]
|
||||||
|
],
|
||||||
|
"text_variables": {}
|
||||||
|
}
|
||||||
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Loading…
Reference in New Issue