mirror of https://codeberg.org/topola/topola.git
test: Add vga_dac_breakout test
This simple breakout board tests routing around SMD pads.
This commit is contained in:
Mikolaj Wielgus
parent
cc6065099b
commit
ff6d00d34a
|
|
@ -123,7 +123,22 @@ fn test_tht_3pin_xlr_to_tht_3pin_xlr() {
|
|||
|
||||
let (mut autorouter, ..) = invoker.dissolve();
|
||||
|
||||
// FIXME: The routing result is pretty bad.
|
||||
common::assert_single_layer_groundless_autoroute(&mut autorouter, "F.Cu");
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn test_vga_dac_breakout() {
|
||||
let mut autorouter =
|
||||
common::load_design("tests/single_layer/vga_dac_breakout/vga_dac_breakout.dsn");
|
||||
common::assert_navnode_count(&mut autorouter, "J1-2", "R4-1", 944);
|
||||
let mut invoker = common::create_invoker_and_assert(autorouter);
|
||||
common::replay_and_assert(
|
||||
&mut invoker,
|
||||
"tests/single_layer/vga_dac_breakout/autoroute_all.cmd",
|
||||
);
|
||||
|
||||
let (mut autorouter, ..) = invoker.dissolve();
|
||||
|
||||
common::assert_single_layer_groundless_autoroute(&mut autorouter, "F.Cu");
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,224 @@
|
|||
{
|
||||
"done": [
|
||||
{
|
||||
"Autoroute": [
|
||||
[
|
||||
{
|
||||
"pin": "J1-0",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "J1-0@1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "J1-1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "J1-10",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "J1-11",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "J1-12",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "J1-13",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "J1-14",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "J1-15",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "J1-2",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "J1-3",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "J1-4",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "J1-5",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "J1-6",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "J1-7",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "J1-8",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "J1-9",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "J2-1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "J2-2",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "J2-3",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "J2-4",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "J2-5",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "J2-6",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "J3-1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "J3-2",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "J3-3",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "J3-4",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "J3-5",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "J3-6",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "R1-1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "R1-2",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "R10-1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "R10-2",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "R11-1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "R11-2",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "R2-1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "R2-2",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "R3-1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "R3-2",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "R4-1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "R4-2",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "R5-1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "R5-2",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "R6-1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "R6-2",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "R7-1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "R7-2",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "R8-1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "R8-2",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "R9-1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "R9-2",
|
||||
"layer": "F.Cu"
|
||||
}
|
||||
],
|
||||
{
|
||||
"presort_by": "RatlineIntersectionCountAndLength",
|
||||
"permutate": true,
|
||||
"router_options": {
|
||||
"routed_band_width": 100.0,
|
||||
"wrap_around_bands": true,
|
||||
"squeeze_through_under_bends": true
|
||||
}
|
||||
}
|
||||
]
|
||||
}
|
||||
],
|
||||
"undone": []
|
||||
}
|
||||
|
|
@ -0,0 +1,697 @@
|
|||
(pcb /home/mikolaj/proj/topola/tests/single_layer/vga_dac_breakout/vga_dac_breakout.dsn
|
||||
(parser
|
||||
(string_quote ")
|
||||
(space_in_quoted_tokens on)
|
||||
(host_cad "KiCad's Pcbnew")
|
||||
(host_version "9.0.2")
|
||||
)
|
||||
(resolution um 10)
|
||||
(unit um)
|
||||
(structure
|
||||
(layer F.Cu
|
||||
(type signal)
|
||||
(property
|
||||
(index 0)
|
||||
)
|
||||
)
|
||||
(layer B.Cu
|
||||
(type signal)
|
||||
(property
|
||||
(index 1)
|
||||
)
|
||||
)
|
||||
(boundary
|
||||
(path pcb 0 166500 -145000 133500 -145000 133500 -103250 166500 -103250
|
||||
166500 -145000)
|
||||
)
|
||||
(via "Via[0-1]_600:300_um")
|
||||
(rule
|
||||
(width 200)
|
||||
(clearance 200)
|
||||
(clearance 50 (type smd_smd))
|
||||
)
|
||||
)
|
||||
(placement
|
||||
(component Resistor_SMD:R_1206_3216Metric
|
||||
(place R9 155962.500000 -115000.000000 front 0.000000 (PN 510))
|
||||
(place R11 154962.500000 -121000.000000 front 0.000000 (PN 200))
|
||||
(place R8 155962.500000 -112500.000000 front 0.000000 (PN 1K))
|
||||
(place R10 155000.000000 -118500.000000 front 0.000000 (PN 200))
|
||||
(place R7 155962.500000 -110000.000000 front 0.000000 (PN 2K))
|
||||
)
|
||||
(component Resistor_SMD:R_1206_3216Metric::1
|
||||
(place R1 144000.000000 -123500.000000 front 180.000000 (PN 2K))
|
||||
(place R5 143955.000000 -112500.000000 front 180.000000 (PN 1K))
|
||||
(place R2 144000.000000 -121000.000000 front 180.000000 (PN 1K))
|
||||
(place R6 143917.500000 -110000.000000 front 180.000000 (PN 510))
|
||||
(place R4 143955.000000 -115000.000000 front 180.000000 (PN 2K))
|
||||
(place R3 144000.000000 -118500.000000 front 180.000000 (PN 510))
|
||||
)
|
||||
(component TerminalBlock_4Ucon:TerminalBlock_4Ucon_1x06_P3.50mm_Vertical
|
||||
(place J2 138250.000000 -108000.000000 back 90.000000 (PN Screw_Terminal_01x06))
|
||||
)
|
||||
(component "Connector_Dsub:DSUB-15-HD_Socket_Horizontal_P2.29x2.54mm_EdgePinOffset8.35mm_Housed_MountingHolesOffset10.89mm"
|
||||
(place J1 145680.000000 -131214.669000 back 0.000000 (PN DE15_Socket_HighDensity_MountingHoles))
|
||||
)
|
||||
(component TerminalBlock_4Ucon:TerminalBlock_4Ucon_1x06_P3.50mm_Vertical::1
|
||||
(place J3 161750.000000 -125500.000000 back 270.000000 (PN Screw_Terminal_01x06))
|
||||
)
|
||||
)
|
||||
(library
|
||||
(image Resistor_SMD:R_1206_3216Metric
|
||||
(outline (path signal 120 -727.064 910 727.064 910))
|
||||
(outline (path signal 120 -727.064 -910 727.064 -910))
|
||||
(outline (path signal 50 -2280 1130 2280 1130))
|
||||
(outline (path signal 50 -2280 -1130 -2280 1130))
|
||||
(outline (path signal 50 2280 1130 2280 -1130))
|
||||
(outline (path signal 50 2280 -1130 -2280 -1130))
|
||||
(outline (path signal 100 -1600 800 1600 800))
|
||||
(outline (path signal 100 -1600 -800 -1600 800))
|
||||
(outline (path signal 100 1600 800 1600 -800))
|
||||
(outline (path signal 100 1600 -800 -1600 -800))
|
||||
(pin RoundRect[T]Pad_1125.000000x1750.000000_250.951000_um_0.000000_0 1 -1462.5 0)
|
||||
(pin RoundRect[T]Pad_1125.000000x1750.000000_250.951000_um_0.000000_0 2 1462.5 0)
|
||||
)
|
||||
(image Resistor_SMD:R_1206_3216Metric::1
|
||||
(outline (path signal 120 -727.064 -910 727.064 -910))
|
||||
(outline (path signal 120 -727.064 910 727.064 910))
|
||||
(outline (path signal 50 2280 -1130 -2280 -1130))
|
||||
(outline (path signal 50 2280 1130 2280 -1130))
|
||||
(outline (path signal 50 -2280 -1130 -2280 1130))
|
||||
(outline (path signal 50 -2280 1130 2280 1130))
|
||||
(outline (path signal 100 1600 -800 -1600 -800))
|
||||
(outline (path signal 100 1600 800 1600 -800))
|
||||
(outline (path signal 100 -1600 -800 -1600 800))
|
||||
(outline (path signal 100 -1600 800 1600 800))
|
||||
(pin RoundRect[T]Pad_1125.000000x1750.000000_250.951000_um_0.000000_0 1 -1462.5 0)
|
||||
(pin RoundRect[T]Pad_1125.000000x1750.000000_250.951000_um_0.000000_0 2 1462.5 0)
|
||||
)
|
||||
(image TerminalBlock_4Ucon:TerminalBlock_4Ucon_1x06_P3.50mm_Vertical
|
||||
(outline (path signal 120 -2370 3820 19870 3820))
|
||||
(outline (path signal 120 -2370 3820 -2370 -4720))
|
||||
(outline (path signal 120 19870 3820 19870 -4720))
|
||||
(outline (path signal 120 -1400 3000 1400 3000))
|
||||
(outline (path signal 120 -1400 3000 -1400 1780))
|
||||
(outline (path signal 120 1400 3000 1400 1780))
|
||||
(outline (path signal 120 2100 3000 4900 3000))
|
||||
(outline (path signal 120 2100 3000 2100 1099))
|
||||
(outline (path signal 120 4900 3000 4900 1099))
|
||||
(outline (path signal 120 5600 3000 8400 3000))
|
||||
(outline (path signal 120 5600 3000 5600 1099))
|
||||
(outline (path signal 120 8400 3000 8400 1099))
|
||||
(outline (path signal 120 9100 3000 11900 3000))
|
||||
(outline (path signal 120 9100 3000 9100 1099))
|
||||
(outline (path signal 120 11900 3000 11900 1099))
|
||||
(outline (path signal 120 12600 3000 15400 3000))
|
||||
(outline (path signal 120 12600 3000 12600 1099))
|
||||
(outline (path signal 120 15400 3000 15400 1099))
|
||||
(outline (path signal 120 16100 3000 18900 3000))
|
||||
(outline (path signal 120 16100 3000 16100 1099))
|
||||
(outline (path signal 120 18900 3000 18900 1099))
|
||||
(outline (path signal 120 -2370 -1100 -1780 -1100))
|
||||
(outline (path signal 120 1780 -1100 2101 -1100))
|
||||
(outline (path signal 120 4899 -1100 5601 -1100))
|
||||
(outline (path signal 120 8399 -1100 9101 -1100))
|
||||
(outline (path signal 120 11899 -1100 12601 -1100))
|
||||
(outline (path signal 120 15399 -1100 16101 -1100))
|
||||
(outline (path signal 120 18899 -1100 19870 -1100))
|
||||
(outline (path signal 120 -2370 -4720 -300 -4720))
|
||||
(outline (path signal 120 300 -4720 19870 -4720))
|
||||
(outline (path signal 0 1039.43 1790.16 1039.43 1757.04 1006.96 1724.57 961.039 1724.57
|
||||
928.567 1757.04 928.567 1769.84 924.984 1769.18 873.38 1948.25
|
||||
787.478 2113.63 670.65 2258.83 527.484 2378.13 363.603 2466.86
|
||||
185.443 2521.53 0 2540 -185.443 2521.53 -363.603 2466.86
|
||||
-527.484 2378.13 -670.65 2258.83 -787.478 2113.63 -873.38 1948.25
|
||||
-924.984 1769.18 -928.567 1769.84 -928.567 1757.04 -961.039 1724.57
|
||||
-1006.96 1724.57 -1039.43 1757.04 -1039.43 1790.16 -1043.02 1790.82
|
||||
-989.944 1979.68 -902.992 2155.53 -785.135 2312.35 -640.407 2444.78
|
||||
-473.762 2548.28 -290.902 2619.32 -98.086 2655.45 98.086 2655.45
|
||||
290.902 2619.32 473.762 2548.28 640.407 2444.78 785.135 2312.35
|
||||
902.992 2155.53 989.944 1979.68 1043.02 1790.82))
|
||||
(outline (path signal 0 4551.55 1470.65 4547.43 1471.16 4547.43 1455.04 4514.96 1422.57
|
||||
4469.04 1422.57 4436.57 1455.04 4436.57 1484.84 4432.45 1485.35
|
||||
4436.79 1672.19 4404.06 1856.2 4335.55 2030.08 4233.99 2186.97
|
||||
4103.38 2320.65 3948.89 2425.83 3776.64 2498.35 3593.45 2535.34
|
||||
3406.55 2535.34 3223.36 2498.35 3051.11 2425.83 2896.62 2320.65
|
||||
2766.01 2186.97 2664.45 2030.08 2595.94 1856.2 2563.21 1672.19
|
||||
2567.55 1485.35 2563.43 1484.84 2563.43 1455.04 2530.96 1422.57
|
||||
2485.04 1422.57 2452.57 1455.04 2452.57 1471.16 2448.45 1470.65
|
||||
2442.73 1669.66 2474.34 1866.22 2542.16 2053.4 2643.8 2224.59
|
||||
2775.67 2373.74 2933.12 2495.6 3110.58 2585.84 3301.79 2641.3
|
||||
3500 2660 3698.21 2641.3 3889.42 2585.84 4066.88 2495.6 4224.33 2373.74
|
||||
4356.2 2224.59 4457.84 2053.4 4525.66 1866.22 4557.27 1669.66))
|
||||
(outline (path signal 0 8051.55 1470.65 8047.43 1471.16 8047.43 1455.04 8014.96 1422.57
|
||||
7969.04 1422.57 7936.57 1455.04 7936.57 1484.84 7932.45 1485.35
|
||||
7936.79 1672.19 7904.06 1856.2 7835.55 2030.08 7733.99 2186.97
|
||||
7603.38 2320.65 7448.89 2425.83 7276.64 2498.35 7093.45 2535.34
|
||||
6906.55 2535.34 6723.36 2498.35 6551.11 2425.83 6396.62 2320.65
|
||||
6266.01 2186.97 6164.45 2030.08 6095.94 1856.2 6063.21 1672.19
|
||||
6067.55 1485.35 6063.43 1484.84 6063.43 1455.04 6030.96 1422.57
|
||||
5985.04 1422.57 5952.57 1455.04 5952.57 1471.16 5948.45 1470.65
|
||||
5942.73 1669.66 5974.34 1866.22 6042.16 2053.4 6143.8 2224.59
|
||||
6275.67 2373.74 6433.12 2495.6 6610.58 2585.84 6801.79 2641.3
|
||||
7000 2660 7198.21 2641.3 7389.42 2585.84 7566.88 2495.6 7724.33 2373.74
|
||||
7856.2 2224.59 7957.84 2053.4 8025.66 1866.22 8057.27 1669.66))
|
||||
(outline (path signal 0 11551.5 1470.65 11547.4 1471.16 11547.4 1455.04 11515 1422.57
|
||||
11469 1422.57 11436.6 1455.04 11436.6 1484.84 11432.5 1485.35
|
||||
11436.8 1672.19 11404.1 1856.2 11335.6 2030.08 11234 2186.97
|
||||
11103.4 2320.65 10948.9 2425.83 10776.6 2498.35 10593.4 2535.34
|
||||
10406.6 2535.34 10223.4 2498.35 10051.1 2425.83 9896.62 2320.65
|
||||
9766.01 2186.97 9664.45 2030.08 9595.94 1856.2 9563.21 1672.19
|
||||
9567.55 1485.35 9563.43 1484.84 9563.43 1455.04 9530.96 1422.57
|
||||
9485.04 1422.57 9452.57 1455.04 9452.57 1471.16 9448.45 1470.65
|
||||
9442.73 1669.66 9474.34 1866.22 9542.16 2053.4 9643.8 2224.59
|
||||
9775.67 2373.74 9933.12 2495.6 10110.6 2585.84 10301.8 2641.3
|
||||
10500 2660 10698.2 2641.3 10889.4 2585.84 11066.9 2495.6
|
||||
11224.3 2373.74 11356.2 2224.59 11457.8 2053.4 11525.7 1866.22
|
||||
11557.3 1669.66))
|
||||
(outline (path signal 0 15051.5 1470.65 15047.4 1471.16 15047.4 1455.04 15015 1422.57
|
||||
14969 1422.57 14936.6 1455.04 14936.6 1484.84 14932.5 1485.35
|
||||
14936.8 1672.19 14904.1 1856.2 14835.6 2030.08 14734 2186.97
|
||||
14603.4 2320.65 14448.9 2425.83 14276.6 2498.35 14093.4 2535.34
|
||||
13906.6 2535.34 13723.4 2498.35 13551.1 2425.83 13396.6 2320.65
|
||||
13266 2186.97 13164.4 2030.08 13095.9 1856.2 13063.2 1672.19
|
||||
13067.5 1485.35 13063.4 1484.84 13063.4 1455.04 13031 1422.57
|
||||
12985 1422.57 12952.6 1455.04 12952.6 1471.16 12948.5 1470.65
|
||||
12942.7 1669.66 12974.3 1866.22 13042.2 2053.4 13143.8 2224.59
|
||||
13275.7 2373.74 13433.1 2495.6 13610.6 2585.84 13801.8 2641.3
|
||||
14000 2660 14198.2 2641.3 14389.4 2585.84 14566.9 2495.6
|
||||
14724.3 2373.74 14856.2 2224.59 14957.8 2053.4 15025.7 1866.22
|
||||
15057.3 1669.66))
|
||||
(outline (path signal 0 18551.5 1470.65 18547.4 1471.16 18547.4 1455.04 18515 1422.57
|
||||
18469 1422.57 18436.6 1455.04 18436.6 1484.84 18432.5 1485.35
|
||||
18436.8 1672.19 18404.1 1856.2 18335.6 2030.08 18234 2186.97
|
||||
18103.4 2320.65 17948.9 2425.83 17776.6 2498.35 17593.4 2535.34
|
||||
17406.6 2535.34 17223.4 2498.35 17051.1 2425.83 16896.6 2320.65
|
||||
16766 2186.97 16664.4 2030.08 16595.9 1856.2 16563.2 1672.19
|
||||
16567.5 1485.35 16563.4 1484.84 16563.4 1455.04 16531 1422.57
|
||||
16485 1422.57 16452.6 1455.04 16452.6 1471.16 16448.5 1470.65
|
||||
16442.7 1669.66 16474.3 1866.22 16542.2 2053.4 16643.8 2224.59
|
||||
16775.7 2373.74 16933.1 2495.6 17110.6 2585.84 17301.8 2641.3
|
||||
17500 2660 17698.2 2641.3 17889.4 2585.84 18066.9 2495.6
|
||||
18224.3 2373.74 18356.2 2224.59 18457.8 2053.4 18525.7 1866.22
|
||||
18557.3 1669.66))
|
||||
(outline (path signal 50 -2750 4200 -2750 -5110))
|
||||
(outline (path signal 50 20250 4200 -2750 4200))
|
||||
(outline (path signal 50 -2750 -5110 20250 -5110))
|
||||
(outline (path signal 50 20250 -5110 20250 4200))
|
||||
(outline (path signal 100 -2250 3700 19750 3700))
|
||||
(outline (path signal 100 19750 3700 19750 -4600))
|
||||
(outline (path signal 100 -1400 3000 -1400 -750))
|
||||
(outline (path signal 100 1400 3000 -1400 3000))
|
||||
(outline (path signal 100 2100 3000 2100 -750))
|
||||
(outline (path signal 100 4900 3000 2100 3000))
|
||||
(outline (path signal 100 5600 3000 5600 -750))
|
||||
(outline (path signal 100 8400 3000 5600 3000))
|
||||
(outline (path signal 100 9100 3000 9100 -750))
|
||||
(outline (path signal 100 11900 3000 9100 3000))
|
||||
(outline (path signal 100 12600 3000 12600 -750))
|
||||
(outline (path signal 100 15400 3000 12600 3000))
|
||||
(outline (path signal 100 16101 3000 16101 -750))
|
||||
(outline (path signal 100 18900 3000 16101 3000))
|
||||
(outline (path signal 100 -1400 -750 1400 -750))
|
||||
(outline (path signal 100 1400 -750 1400 3000))
|
||||
(outline (path signal 100 2100 -750 4900 -750))
|
||||
(outline (path signal 100 4900 -750 4900 3000))
|
||||
(outline (path signal 100 5600 -750 8400 -750))
|
||||
(outline (path signal 100 8400 -750 8400 3000))
|
||||
(outline (path signal 100 9100 -750 11900 -750))
|
||||
(outline (path signal 100 11900 -750 11900 3000))
|
||||
(outline (path signal 100 12600 -750 15400 -750))
|
||||
(outline (path signal 100 15400 -750 15400 3000))
|
||||
(outline (path signal 100 16101 -750 18900 -750))
|
||||
(outline (path signal 100 18900 -750 18900 3000))
|
||||
(outline (path signal 100 -2250 -1100 19750 -1100))
|
||||
(outline (path signal 100 -2250 -2600 -2250 3700))
|
||||
(outline (path signal 100 -250 -4600 -2250 -2600))
|
||||
(outline (path signal 100 19750 -4600 -250 -4600))
|
||||
(outline (path signal 100 0 600 -195.09 619.215 -382.683 676.12 -555.57 768.53
|
||||
-707.107 892.893 -831.47 1044.43 -923.88 1217.32 -980.785 1404.91
|
||||
-1000 1600 -980.785 1795.09 -923.88 1982.68 -831.47 2155.57
|
||||
-707.107 2307.11 -555.57 2431.47 -382.683 2523.88 -195.09 2580.78
|
||||
0 2600 195.09 2580.78 382.683 2523.88 555.57 2431.47 707.107 2307.11
|
||||
831.47 2155.57 923.88 1982.68 980.785 1795.09 1000 1600 980.785 1404.91
|
||||
923.88 1217.32 831.47 1044.43 707.107 892.893 555.57 768.53
|
||||
382.683 676.12 195.09 619.215 0 600))
|
||||
(outline (path signal 100 3500 600 3304.91 619.215 3117.32 676.12 2944.43 768.53
|
||||
2792.89 892.893 2668.53 1044.43 2576.12 1217.32 2519.22 1404.91
|
||||
2500 1600 2519.22 1795.09 2576.12 1982.68 2668.53 2155.57
|
||||
2792.89 2307.11 2944.43 2431.47 3117.32 2523.88 3304.91 2580.78
|
||||
3500 2600 3695.09 2580.78 3882.68 2523.88 4055.57 2431.47
|
||||
4207.11 2307.11 4331.47 2155.57 4423.88 1982.68 4480.78 1795.09
|
||||
4500 1600 4480.78 1404.91 4423.88 1217.32 4331.47 1044.43
|
||||
4207.11 892.893 4055.57 768.53 3882.68 676.12 3695.09 619.215
|
||||
3500 600))
|
||||
(outline (path signal 100 7000 600 6804.91 619.215 6617.32 676.12 6444.43 768.53
|
||||
6292.89 892.893 6168.53 1044.43 6076.12 1217.32 6019.22 1404.91
|
||||
6000 1600 6019.22 1795.09 6076.12 1982.68 6168.53 2155.57
|
||||
6292.89 2307.11 6444.43 2431.47 6617.32 2523.88 6804.91 2580.78
|
||||
7000 2600 7195.09 2580.78 7382.68 2523.88 7555.57 2431.47
|
||||
7707.11 2307.11 7831.47 2155.57 7923.88 1982.68 7980.78 1795.09
|
||||
8000 1600 7980.78 1404.91 7923.88 1217.32 7831.47 1044.43
|
||||
7707.11 892.893 7555.57 768.53 7382.68 676.12 7195.09 619.215
|
||||
7000 600))
|
||||
(outline (path signal 100 10500 600 10304.9 619.215 10117.3 676.12 9944.43 768.53
|
||||
9792.89 892.893 9668.53 1044.43 9576.12 1217.32 9519.22 1404.91
|
||||
9500 1600 9519.22 1795.09 9576.12 1982.68 9668.53 2155.57
|
||||
9792.89 2307.11 9944.43 2431.47 10117.3 2523.88 10304.9 2580.78
|
||||
10500 2600 10695.1 2580.78 10882.7 2523.88 11055.6 2431.47
|
||||
11207.1 2307.11 11331.5 2155.57 11423.9 1982.68 11480.8 1795.09
|
||||
11500 1600 11480.8 1404.91 11423.9 1217.32 11331.5 1044.43
|
||||
11207.1 892.893 11055.6 768.53 10882.7 676.12 10695.1 619.215
|
||||
10500 600))
|
||||
(outline (path signal 100 14000 600 13804.9 619.215 13617.3 676.12 13444.4 768.53
|
||||
13292.9 892.893 13168.5 1044.43 13076.1 1217.32 13019.2 1404.91
|
||||
13000 1600 13019.2 1795.09 13076.1 1982.68 13168.5 2155.57
|
||||
13292.9 2307.11 13444.4 2431.47 13617.3 2523.88 13804.9 2580.78
|
||||
14000 2600 14195.1 2580.78 14382.7 2523.88 14555.6 2431.47
|
||||
14707.1 2307.11 14831.5 2155.57 14923.9 1982.68 14980.8 1795.09
|
||||
15000 1600 14980.8 1404.91 14923.9 1217.32 14831.5 1044.43
|
||||
14707.1 892.893 14555.6 768.53 14382.7 676.12 14195.1 619.215
|
||||
14000 600))
|
||||
(outline (path signal 100 17500 600 17304.9 619.215 17117.3 676.12 16944.4 768.53
|
||||
16792.9 892.893 16668.5 1044.43 16576.1 1217.32 16519.2 1404.91
|
||||
16500 1600 16519.2 1795.09 16576.1 1982.68 16668.5 2155.57
|
||||
16792.9 2307.11 16944.4 2431.47 17117.3 2523.88 17304.9 2580.78
|
||||
17500 2600 17695.1 2580.78 17882.7 2523.88 18055.6 2431.47
|
||||
18207.1 2307.11 18331.5 2155.57 18423.9 1982.68 18480.8 1795.09
|
||||
18500 1600 18480.8 1404.91 18423.9 1217.32 18331.5 1044.43
|
||||
18207.1 892.893 18055.6 768.53 17882.7 676.12 17695.1 619.215
|
||||
17500 600))
|
||||
(pin RoundRect[A]Pad_2600.000000x2600.000000_250.951000_um_0.000000_0 1 0 0)
|
||||
(pin Round[A]Pad_2600.000000_um 2 3500 0)
|
||||
(pin Round[A]Pad_2600.000000_um 3 7000 0)
|
||||
(pin Round[A]Pad_2600.000000_um 4 10500 0)
|
||||
(pin Round[A]Pad_2600.000000_um 5 14000 0)
|
||||
(pin Round[A]Pad_2600.000000_um 6 17500 0)
|
||||
)
|
||||
(image "Connector_Dsub:DSUB-15-HD_Socket_Horizontal_P2.29x2.54mm_EdgePinOffset8.35mm_Housed_MountingHolesOffset10.89mm"
|
||||
(outline (path signal 120 11170 1830 11170 -13370))
|
||||
(outline (path signal 120 250 2724.34 0 2291.32))
|
||||
(outline (path signal 120 0 2291.32 -250 2724.34))
|
||||
(outline (path signal 120 -250 2724.34 250 2724.34))
|
||||
(outline (path signal 120 -19800 1830 11170 1830))
|
||||
(outline (path signal 120 -19800 -13370 -19800 1830))
|
||||
(outline (path signal 50 11610 2270 -20250 2270))
|
||||
(outline (path signal 50 11610 -20330 11610 2270))
|
||||
(outline (path signal 50 -20250 2270 -20250 -20330))
|
||||
(outline (path signal 50 -20250 -20330 11610 -20330))
|
||||
(outline (path signal 100 11110 1770 -19740 1770))
|
||||
(outline (path signal 100 11110 -13430 11110 1770))
|
||||
(outline (path signal 100 11110 -13430 -19740 -13430))
|
||||
(outline (path signal 100 11110 -13830 11110 -13430))
|
||||
(outline (path signal 100 10685 -13830 5685 -13830))
|
||||
(outline (path signal 100 10685 -18830 10685 -13830))
|
||||
(outline (path signal 100 9785 -13430 9785 -2540))
|
||||
(outline (path signal 100 6585 -13430 6585 -2540))
|
||||
(outline (path signal 100 5685 -13830 5685 -18830))
|
||||
(outline (path signal 100 5685 -18830 10685 -18830))
|
||||
(outline (path signal 100 3835 -13830 -12465 -13830))
|
||||
(outline (path signal 100 3835 -19830 3835 -13830))
|
||||
(outline (path signal 100 -12465 -13830 -12465 -19830))
|
||||
(outline (path signal 100 -12465 -19830 3835 -19830))
|
||||
(outline (path signal 100 -14315 -13830 -19315 -13830))
|
||||
(outline (path signal 100 -14315 -18830 -14315 -13830))
|
||||
(outline (path signal 100 -15215 -13430 -15215 -2540))
|
||||
(outline (path signal 100 -18415 -13430 -18415 -2540))
|
||||
(outline (path signal 100 -19315 -13830 -19315 -18830))
|
||||
(outline (path signal 100 -19315 -18830 -14315 -18830))
|
||||
(outline (path signal 100 -19740 1770 -19740 -13430))
|
||||
(outline (path signal 100 -19740 -13430 11110 -13430))
|
||||
(outline (path signal 100 -19740 -13430 -19740 -13830))
|
||||
(outline (path signal 100 -19740 -13830 11110 -13830))
|
||||
(outline (path signal 0 9738.81 -2559.13 9738.81 -2540 9735 -2540 9717.69 -2308.98
|
||||
9666.14 -2083.13 9581.5 -1867.48 9465.67 -1666.85 9321.23 -1485.73
|
||||
9151.41 -1328.16 8960 -1197.66 8751.28 -1097.15 8529.91 -1028.86
|
||||
8300.83 -994.334 8069.17 -994.334 7840.09 -1028.86 7618.72 -1097.15
|
||||
7410 -1197.66 7218.59 -1328.16 7048.77 -1485.73 6904.33 -1666.85
|
||||
6788.5 -1867.48 6703.86 -2083.13 6652.31 -2308.98 6635 -2540
|
||||
6631.19 -2540 6631.19 -2559.13 6604.13 -2586.19 6565.87 -2586.19
|
||||
6538.81 -2559.13 6538.81 -2540 6535 -2540 6553.43 -2294.08
|
||||
6608.31 -2053.65 6698.4 -1824.09 6821.71 -1610.52 6975.46 -1417.71
|
||||
7156.24 -1249.98 7360 -1111.06 7582.19 -1004.06 7817.84 -931.369
|
||||
8061.69 -894.614 8308.31 -894.614 8552.16 -931.369 8787.81 -1004.06
|
||||
9010 -1111.06 9213.76 -1249.98 9394.54 -1417.71 9548.29 -1610.52
|
||||
9671.6 -1824.09 9761.69 -2053.65 9816.57 -2294.08 9835 -2540
|
||||
9831.19 -2540 9831.19 -2559.13 9804.13 -2586.19 9765.87 -2586.19))
|
||||
(outline (path signal 0 -15261.2 -2559.13 -15261.2 -2540 -15265 -2540 -15282.3 -2308.98
|
||||
-15333.9 -2083.13 -15418.5 -1867.48 -15534.3 -1666.85 -15678.8 -1485.73
|
||||
-15848.6 -1328.16 -16040 -1197.66 -16248.7 -1097.15 -16470.1 -1028.86
|
||||
-16699.2 -994.334 -16930.8 -994.334 -17159.9 -1028.86 -17381.3 -1097.15
|
||||
-17590 -1197.66 -17781.4 -1328.16 -17951.2 -1485.73 -18095.7 -1666.85
|
||||
-18211.5 -1867.48 -18296.1 -2083.13 -18347.7 -2308.98 -18365 -2540
|
||||
-18368.8 -2540 -18368.8 -2559.13 -18395.9 -2586.19 -18434.1 -2586.19
|
||||
-18461.2 -2559.13 -18461.2 -2540 -18465 -2540 -18446.6 -2294.08
|
||||
-18391.7 -2053.65 -18301.6 -1824.09 -18178.3 -1610.52 -18024.5 -1417.71
|
||||
-17843.8 -1249.98 -17640 -1111.06 -17417.8 -1004.06 -17182.2 -931.369
|
||||
-16938.3 -894.614 -16691.7 -894.614 -16447.8 -931.369 -16212.2 -1004.06
|
||||
-15990 -1111.06 -15786.2 -1249.98 -15605.5 -1417.71 -15451.7 -1610.52
|
||||
-15328.4 -1824.09 -15238.3 -2053.65 -15183.4 -2294.08 -15165 -2540
|
||||
-15168.8 -2540 -15168.8 -2559.13 -15195.9 -2586.19 -15234.1 -2586.19))
|
||||
(pin Round[A]Pad_4000.000000_um 0 -16815 -2540)
|
||||
(pin Round[A]Pad_4000.000000_um 0@1 8185 -2540)
|
||||
(pin Rect[A]Pad_1600.000000x1600.000000_um 1 0 0)
|
||||
(pin Round[A]Pad_1600.000000_um 2 -2290 0)
|
||||
(pin Round[A]Pad_1600.000000_um 3 -4580 0)
|
||||
(pin Round[A]Pad_1600.000000_um 4 -6870 0)
|
||||
(pin Round[A]Pad_1600.000000_um 5 -9160 0)
|
||||
(pin Round[A]Pad_1600.000000_um 6 1145 -2540)
|
||||
(pin Round[A]Pad_1600.000000_um 7 -1145 -2540)
|
||||
(pin Round[A]Pad_1600.000000_um 8 -3435 -2540)
|
||||
(pin Round[A]Pad_1600.000000_um 9 -5725 -2540)
|
||||
(pin Round[A]Pad_1600.000000_um 10 -8015 -2540)
|
||||
(pin Round[A]Pad_1600.000000_um 11 0 -5080)
|
||||
(pin Round[A]Pad_1600.000000_um 12 -2290 -5080)
|
||||
(pin Round[A]Pad_1600.000000_um 13 -4580 -5080)
|
||||
(pin Round[A]Pad_1600.000000_um 14 -6870 -5080)
|
||||
(pin Round[A]Pad_1600.000000_um 15 -9160 -5080)
|
||||
)
|
||||
(image TerminalBlock_4Ucon:TerminalBlock_4Ucon_1x06_P3.50mm_Vertical::1
|
||||
(outline (path signal 120 300 -4720 19870 -4720))
|
||||
(outline (path signal 120 -2370 -4720 -300 -4720))
|
||||
(outline (path signal 120 18899 -1100 19870 -1100))
|
||||
(outline (path signal 120 15399 -1100 16101 -1100))
|
||||
(outline (path signal 120 11899 -1100 12601 -1100))
|
||||
(outline (path signal 120 8399 -1100 9101 -1100))
|
||||
(outline (path signal 120 4899 -1100 5601 -1100))
|
||||
(outline (path signal 120 1780 -1100 2101 -1100))
|
||||
(outline (path signal 120 -2370 -1100 -1780 -1100))
|
||||
(outline (path signal 120 18900 3000 18900 1099))
|
||||
(outline (path signal 120 16100 3000 16100 1099))
|
||||
(outline (path signal 120 16100 3000 18900 3000))
|
||||
(outline (path signal 120 15400 3000 15400 1099))
|
||||
(outline (path signal 120 12600 3000 12600 1099))
|
||||
(outline (path signal 120 12600 3000 15400 3000))
|
||||
(outline (path signal 120 11900 3000 11900 1099))
|
||||
(outline (path signal 120 9100 3000 9100 1099))
|
||||
(outline (path signal 120 9100 3000 11900 3000))
|
||||
(outline (path signal 120 8400 3000 8400 1099))
|
||||
(outline (path signal 120 5600 3000 5600 1099))
|
||||
(outline (path signal 120 5600 3000 8400 3000))
|
||||
(outline (path signal 120 4900 3000 4900 1099))
|
||||
(outline (path signal 120 2100 3000 2100 1099))
|
||||
(outline (path signal 120 2100 3000 4900 3000))
|
||||
(outline (path signal 120 1400 3000 1400 1780))
|
||||
(outline (path signal 120 -1400 3000 -1400 1780))
|
||||
(outline (path signal 120 -1400 3000 1400 3000))
|
||||
(outline (path signal 120 19870 3820 19870 -4720))
|
||||
(outline (path signal 120 -2370 3820 -2370 -4720))
|
||||
(outline (path signal 120 -2370 3820 19870 3820))
|
||||
(outline (path signal 0 16474.3 1866.22 16542.2 2053.4 16643.8 2224.59 16775.7 2373.74
|
||||
16933.1 2495.6 17110.6 2585.84 17301.8 2641.3 17500 2660
|
||||
17698.2 2641.3 17889.4 2585.84 18066.9 2495.6 18224.3 2373.74
|
||||
18356.2 2224.59 18457.8 2053.4 18525.7 1866.22 18557.3 1669.66
|
||||
18551.5 1470.65 18547.4 1471.16 18547.4 1455.04 18515 1422.57
|
||||
18469 1422.57 18436.6 1455.04 18436.6 1484.84 18432.5 1485.35
|
||||
18436.8 1672.19 18404.1 1856.2 18335.6 2030.08 18234 2186.97
|
||||
18103.4 2320.65 17948.9 2425.83 17776.6 2498.35 17593.4 2535.34
|
||||
17406.6 2535.34 17223.4 2498.35 17051.1 2425.83 16896.6 2320.65
|
||||
16766 2186.97 16664.4 2030.08 16595.9 1856.2 16563.2 1672.19
|
||||
16567.5 1485.35 16563.4 1484.84 16563.4 1455.04 16531 1422.57
|
||||
16485 1422.57 16452.6 1455.04 16452.6 1471.16 16448.5 1470.65
|
||||
16442.7 1669.66))
|
||||
(outline (path signal 0 12974.3 1866.22 13042.2 2053.4 13143.8 2224.59 13275.7 2373.74
|
||||
13433.1 2495.6 13610.6 2585.84 13801.8 2641.3 14000 2660
|
||||
14198.2 2641.3 14389.4 2585.84 14566.9 2495.6 14724.3 2373.74
|
||||
14856.2 2224.59 14957.8 2053.4 15025.7 1866.22 15057.3 1669.66
|
||||
15051.5 1470.65 15047.4 1471.16 15047.4 1455.04 15015 1422.57
|
||||
14969 1422.57 14936.6 1455.04 14936.6 1484.84 14932.5 1485.35
|
||||
14936.8 1672.19 14904.1 1856.2 14835.6 2030.08 14734 2186.97
|
||||
14603.4 2320.65 14448.9 2425.83 14276.6 2498.35 14093.4 2535.34
|
||||
13906.6 2535.34 13723.4 2498.35 13551.1 2425.83 13396.6 2320.65
|
||||
13266 2186.97 13164.4 2030.08 13095.9 1856.2 13063.2 1672.19
|
||||
13067.5 1485.35 13063.4 1484.84 13063.4 1455.04 13031 1422.57
|
||||
12985 1422.57 12952.6 1455.04 12952.6 1471.16 12948.5 1470.65
|
||||
12942.7 1669.66))
|
||||
(outline (path signal 0 9474.34 1866.22 9542.16 2053.4 9643.8 2224.59 9775.67 2373.74
|
||||
9933.12 2495.6 10110.6 2585.84 10301.8 2641.3 10500 2660
|
||||
10698.2 2641.3 10889.4 2585.84 11066.9 2495.6 11224.3 2373.74
|
||||
11356.2 2224.59 11457.8 2053.4 11525.7 1866.22 11557.3 1669.66
|
||||
11551.5 1470.65 11547.4 1471.16 11547.4 1455.04 11515 1422.57
|
||||
11469 1422.57 11436.6 1455.04 11436.6 1484.84 11432.5 1485.35
|
||||
11436.8 1672.19 11404.1 1856.2 11335.6 2030.08 11234 2186.97
|
||||
11103.4 2320.65 10948.9 2425.83 10776.6 2498.35 10593.4 2535.34
|
||||
10406.6 2535.34 10223.4 2498.35 10051.1 2425.83 9896.62 2320.65
|
||||
9766.01 2186.97 9664.45 2030.08 9595.94 1856.2 9563.21 1672.19
|
||||
9567.55 1485.35 9563.43 1484.84 9563.43 1455.04 9530.96 1422.57
|
||||
9485.04 1422.57 9452.57 1455.04 9452.57 1471.16 9448.45 1470.65
|
||||
9442.73 1669.66))
|
||||
(outline (path signal 0 5974.34 1866.22 6042.16 2053.4 6143.8 2224.59 6275.67 2373.74
|
||||
6433.12 2495.6 6610.58 2585.84 6801.79 2641.3 7000 2660 7198.21 2641.3
|
||||
7389.42 2585.84 7566.88 2495.6 7724.33 2373.74 7856.2 2224.59
|
||||
7957.84 2053.4 8025.66 1866.22 8057.27 1669.66 8051.55 1470.65
|
||||
8047.43 1471.16 8047.43 1455.04 8014.96 1422.57 7969.04 1422.57
|
||||
7936.57 1455.04 7936.57 1484.84 7932.45 1485.35 7936.79 1672.19
|
||||
7904.06 1856.2 7835.55 2030.08 7733.99 2186.97 7603.38 2320.65
|
||||
7448.89 2425.83 7276.64 2498.35 7093.45 2535.34 6906.55 2535.34
|
||||
6723.36 2498.35 6551.11 2425.83 6396.62 2320.65 6266.01 2186.97
|
||||
6164.45 2030.08 6095.94 1856.2 6063.21 1672.19 6067.55 1485.35
|
||||
6063.43 1484.84 6063.43 1455.04 6030.96 1422.57 5985.04 1422.57
|
||||
5952.57 1455.04 5952.57 1471.16 5948.45 1470.65 5942.73 1669.66))
|
||||
(outline (path signal 0 2474.34 1866.22 2542.16 2053.4 2643.8 2224.59 2775.67 2373.74
|
||||
2933.12 2495.6 3110.58 2585.84 3301.79 2641.3 3500 2660 3698.21 2641.3
|
||||
3889.42 2585.84 4066.88 2495.6 4224.33 2373.74 4356.2 2224.59
|
||||
4457.84 2053.4 4525.66 1866.22 4557.27 1669.66 4551.55 1470.65
|
||||
4547.43 1471.16 4547.43 1455.04 4514.96 1422.57 4469.04 1422.57
|
||||
4436.57 1455.04 4436.57 1484.84 4432.45 1485.35 4436.79 1672.19
|
||||
4404.06 1856.2 4335.55 2030.08 4233.99 2186.97 4103.38 2320.65
|
||||
3948.89 2425.83 3776.64 2498.35 3593.45 2535.34 3406.55 2535.34
|
||||
3223.36 2498.35 3051.11 2425.83 2896.62 2320.65 2766.01 2186.97
|
||||
2664.45 2030.08 2595.94 1856.2 2563.21 1672.19 2567.55 1485.35
|
||||
2563.43 1484.84 2563.43 1455.04 2530.96 1422.57 2485.04 1422.57
|
||||
2452.57 1455.04 2452.57 1471.16 2448.45 1470.65 2442.73 1669.66))
|
||||
(outline (path signal 0 -989.944 1979.68 -902.992 2155.53 -785.135 2312.35 -640.407 2444.78
|
||||
-473.762 2548.28 -290.902 2619.32 -98.086 2655.45 98.086 2655.45
|
||||
290.902 2619.32 473.762 2548.28 640.407 2444.78 785.135 2312.35
|
||||
902.992 2155.53 989.944 1979.68 1043.02 1790.82 1039.43 1790.16
|
||||
1039.43 1757.04 1006.96 1724.57 961.039 1724.57 928.567 1757.04
|
||||
928.567 1769.84 924.984 1769.18 873.38 1948.25 787.478 2113.63
|
||||
670.65 2258.83 527.484 2378.13 363.603 2466.86 185.443 2521.53
|
||||
0 2540 -185.443 2521.53 -363.603 2466.86 -527.484 2378.13
|
||||
-670.65 2258.83 -787.478 2113.63 -873.38 1948.25 -924.984 1769.18
|
||||
-928.567 1769.84 -928.567 1757.04 -961.039 1724.57 -1006.96 1724.57
|
||||
-1039.43 1757.04 -1039.43 1790.16 -1043.02 1790.82))
|
||||
(outline (path signal 50 20250 -5110 20250 4200))
|
||||
(outline (path signal 50 -2750 -5110 20250 -5110))
|
||||
(outline (path signal 50 20250 4200 -2750 4200))
|
||||
(outline (path signal 50 -2750 4200 -2750 -5110))
|
||||
(outline (path signal 100 19750 -4600 -250 -4600))
|
||||
(outline (path signal 100 -250 -4600 -2250 -2600))
|
||||
(outline (path signal 100 -2250 -2600 -2250 3700))
|
||||
(outline (path signal 100 -2250 -1100 19750 -1100))
|
||||
(outline (path signal 100 18900 -750 18900 3000))
|
||||
(outline (path signal 100 16101 -750 18900 -750))
|
||||
(outline (path signal 100 15400 -750 15400 3000))
|
||||
(outline (path signal 100 12600 -750 15400 -750))
|
||||
(outline (path signal 100 11900 -750 11900 3000))
|
||||
(outline (path signal 100 9100 -750 11900 -750))
|
||||
(outline (path signal 100 8400 -750 8400 3000))
|
||||
(outline (path signal 100 5600 -750 8400 -750))
|
||||
(outline (path signal 100 4900 -750 4900 3000))
|
||||
(outline (path signal 100 2100 -750 4900 -750))
|
||||
(outline (path signal 100 1400 -750 1400 3000))
|
||||
(outline (path signal 100 -1400 -750 1400 -750))
|
||||
(outline (path signal 100 18900 3000 16101 3000))
|
||||
(outline (path signal 100 16101 3000 16101 -750))
|
||||
(outline (path signal 100 15400 3000 12600 3000))
|
||||
(outline (path signal 100 12600 3000 12600 -750))
|
||||
(outline (path signal 100 11900 3000 9100 3000))
|
||||
(outline (path signal 100 9100 3000 9100 -750))
|
||||
(outline (path signal 100 8400 3000 5600 3000))
|
||||
(outline (path signal 100 5600 3000 5600 -750))
|
||||
(outline (path signal 100 4900 3000 2100 3000))
|
||||
(outline (path signal 100 2100 3000 2100 -750))
|
||||
(outline (path signal 100 1400 3000 -1400 3000))
|
||||
(outline (path signal 100 -1400 3000 -1400 -750))
|
||||
(outline (path signal 100 19750 3700 19750 -4600))
|
||||
(outline (path signal 100 -2250 3700 19750 3700))
|
||||
(outline (path signal 100 17500 2600 17695.1 2580.78 17882.7 2523.88 18055.6 2431.47
|
||||
18207.1 2307.11 18331.5 2155.57 18423.9 1982.68 18480.8 1795.09
|
||||
18500 1600 18480.8 1404.91 18423.9 1217.32 18331.5 1044.43
|
||||
18207.1 892.893 18055.6 768.53 17882.7 676.12 17695.1 619.215
|
||||
17500 600 17304.9 619.215 17117.3 676.12 16944.4 768.53 16792.9 892.893
|
||||
16668.5 1044.43 16576.1 1217.32 16519.2 1404.91 16500 1600
|
||||
16519.2 1795.09 16576.1 1982.68 16668.5 2155.57 16792.9 2307.11
|
||||
16944.4 2431.47 17117.3 2523.88 17304.9 2580.78 17500 2600))
|
||||
(outline (path signal 100 14000 2600 14195.1 2580.78 14382.7 2523.88 14555.6 2431.47
|
||||
14707.1 2307.11 14831.5 2155.57 14923.9 1982.68 14980.8 1795.09
|
||||
15000 1600 14980.8 1404.91 14923.9 1217.32 14831.5 1044.43
|
||||
14707.1 892.893 14555.6 768.53 14382.7 676.12 14195.1 619.215
|
||||
14000 600 13804.9 619.215 13617.3 676.12 13444.4 768.53 13292.9 892.893
|
||||
13168.5 1044.43 13076.1 1217.32 13019.2 1404.91 13000 1600
|
||||
13019.2 1795.09 13076.1 1982.68 13168.5 2155.57 13292.9 2307.11
|
||||
13444.4 2431.47 13617.3 2523.88 13804.9 2580.78 14000 2600))
|
||||
(outline (path signal 100 10500 2600 10695.1 2580.78 10882.7 2523.88 11055.6 2431.47
|
||||
11207.1 2307.11 11331.5 2155.57 11423.9 1982.68 11480.8 1795.09
|
||||
11500 1600 11480.8 1404.91 11423.9 1217.32 11331.5 1044.43
|
||||
11207.1 892.893 11055.6 768.53 10882.7 676.12 10695.1 619.215
|
||||
10500 600 10304.9 619.215 10117.3 676.12 9944.43 768.53 9792.89 892.893
|
||||
9668.53 1044.43 9576.12 1217.32 9519.22 1404.91 9500 1600
|
||||
9519.22 1795.09 9576.12 1982.68 9668.53 2155.57 9792.89 2307.11
|
||||
9944.43 2431.47 10117.3 2523.88 10304.9 2580.78 10500 2600))
|
||||
(outline (path signal 100 7000 2600 7195.09 2580.78 7382.68 2523.88 7555.57 2431.47
|
||||
7707.11 2307.11 7831.47 2155.57 7923.88 1982.68 7980.78 1795.09
|
||||
8000 1600 7980.78 1404.91 7923.88 1217.32 7831.47 1044.43
|
||||
7707.11 892.893 7555.57 768.53 7382.68 676.12 7195.09 619.215
|
||||
7000 600 6804.91 619.215 6617.32 676.12 6444.43 768.53 6292.89 892.893
|
||||
6168.53 1044.43 6076.12 1217.32 6019.22 1404.91 6000 1600
|
||||
6019.22 1795.09 6076.12 1982.68 6168.53 2155.57 6292.89 2307.11
|
||||
6444.43 2431.47 6617.32 2523.88 6804.91 2580.78 7000 2600))
|
||||
(outline (path signal 100 3500 2600 3695.09 2580.78 3882.68 2523.88 4055.57 2431.47
|
||||
4207.11 2307.11 4331.47 2155.57 4423.88 1982.68 4480.78 1795.09
|
||||
4500 1600 4480.78 1404.91 4423.88 1217.32 4331.47 1044.43
|
||||
4207.11 892.893 4055.57 768.53 3882.68 676.12 3695.09 619.215
|
||||
3500 600 3304.91 619.215 3117.32 676.12 2944.43 768.53 2792.89 892.893
|
||||
2668.53 1044.43 2576.12 1217.32 2519.22 1404.91 2500 1600
|
||||
2519.22 1795.09 2576.12 1982.68 2668.53 2155.57 2792.89 2307.11
|
||||
2944.43 2431.47 3117.32 2523.88 3304.91 2580.78 3500 2600))
|
||||
(outline (path signal 100 0 2600 195.09 2580.78 382.683 2523.88 555.57 2431.47
|
||||
707.107 2307.11 831.47 2155.57 923.88 1982.68 980.785 1795.09
|
||||
1000 1600 980.785 1404.91 923.88 1217.32 831.47 1044.43 707.107 892.893
|
||||
555.57 768.53 382.683 676.12 195.09 619.215 0 600 -195.09 619.215
|
||||
-382.683 676.12 -555.57 768.53 -707.107 892.893 -831.47 1044.43
|
||||
-923.88 1217.32 -980.785 1404.91 -1000 1600 -980.785 1795.09
|
||||
-923.88 1982.68 -831.47 2155.57 -707.107 2307.11 -555.57 2431.47
|
||||
-382.683 2523.88 -195.09 2580.78 0 2600))
|
||||
(pin RoundRect[A]Pad_2600.000000x2600.000000_250.951000_um_0.000000_0 1 0 0)
|
||||
(pin Round[A]Pad_2600.000000_um 2 3500 0)
|
||||
(pin Round[A]Pad_2600.000000_um 3 7000 0)
|
||||
(pin Round[A]Pad_2600.000000_um 4 10500 0)
|
||||
(pin Round[A]Pad_2600.000000_um 5 14000 0)
|
||||
(pin Round[A]Pad_2600.000000_um 6 17500 0)
|
||||
)
|
||||
(padstack Round[A]Pad_1600.000000_um
|
||||
(shape (circle F.Cu 1600))
|
||||
(shape (circle B.Cu 1600))
|
||||
(attach off)
|
||||
)
|
||||
(padstack Round[A]Pad_2600.000000_um
|
||||
(shape (circle F.Cu 2600))
|
||||
(shape (circle B.Cu 2600))
|
||||
(attach off)
|
||||
)
|
||||
(padstack Round[A]Pad_4000.000000_um
|
||||
(shape (circle F.Cu 4000))
|
||||
(shape (circle B.Cu 4000))
|
||||
(attach off)
|
||||
)
|
||||
(padstack RoundRect[A]Pad_2600.000000x2600.000000_250.951000_um_0.000000_0
|
||||
(shape (polygon F.Cu 0 -1300.95 1050 -1281.85 1146.04 -1227.45 1227.45 -1146.04 1281.85
|
||||
-1050 1300.95 1050 1300.95 1146.04 1281.85 1227.45 1227.45
|
||||
1281.85 1146.04 1300.95 1050 1300.95 -1050 1281.85 -1146.04
|
||||
1227.45 -1227.45 1146.04 -1281.85 1050 -1300.95 -1050 -1300.95
|
||||
-1146.04 -1281.85 -1227.45 -1227.45 -1281.85 -1146.04 -1300.95 -1050
|
||||
-1300.95 1050))
|
||||
(shape (polygon B.Cu 0 -1300.95 1050 -1281.85 1146.04 -1227.45 1227.45 -1146.04 1281.85
|
||||
-1050 1300.95 1050 1300.95 1146.04 1281.85 1227.45 1227.45
|
||||
1281.85 1146.04 1300.95 1050 1300.95 -1050 1281.85 -1146.04
|
||||
1227.45 -1227.45 1146.04 -1281.85 1050 -1300.95 -1050 -1300.95
|
||||
-1146.04 -1281.85 -1227.45 -1227.45 -1281.85 -1146.04 -1300.95 -1050
|
||||
-1300.95 1050))
|
||||
(attach off)
|
||||
)
|
||||
(padstack RoundRect[T]Pad_1125.000000x1750.000000_250.951000_um_0.000000_0
|
||||
(shape (polygon F.Cu 0 -563.451 625 -544.348 721.035 -489.949 802.449 -408.535 856.848
|
||||
-312.499 875.95 312.5 875.951 408.535 856.848 489.949 802.449
|
||||
544.348 721.035 563.45 624.999 563.451 -625 544.348 -721.035
|
||||
489.949 -802.449 408.535 -856.848 312.499 -875.95 -312.5 -875.951
|
||||
-408.535 -856.848 -489.949 -802.449 -544.348 -721.035 -563.45 -624.999
|
||||
-563.451 625))
|
||||
(attach off)
|
||||
)
|
||||
(padstack Rect[A]Pad_1600.000000x1600.000000_um
|
||||
(shape (rect F.Cu -800 -800 800 800))
|
||||
(shape (rect B.Cu -800 -800 800 800))
|
||||
(attach off)
|
||||
)
|
||||
(padstack "Via[0-1]_600:300_um"
|
||||
(shape (circle F.Cu 600))
|
||||
(shape (circle B.Cu 600))
|
||||
(attach off)
|
||||
)
|
||||
)
|
||||
(network
|
||||
(net "unconnected-(J1-Pad4)"
|
||||
(pins J1-4)
|
||||
)
|
||||
(net "Net-(J3-Pin_1)"
|
||||
(pins J1-0 J1-0@1 J1-5 J1-6 J1-7 J1-8 J1-10 J3-1)
|
||||
)
|
||||
(net "unconnected-(J1-Pad11)"
|
||||
(pins J1-11)
|
||||
)
|
||||
(net "unconnected-(J1-Pad9)"
|
||||
(pins J1-9)
|
||||
)
|
||||
(net "unconnected-(J1-Pad12)"
|
||||
(pins J1-12)
|
||||
)
|
||||
(net "unconnected-(J1-Pad15)"
|
||||
(pins J1-15)
|
||||
)
|
||||
(net "Net-(J1-Pad2)"
|
||||
(pins R5-1 R6-1 R4-1 J1-2)
|
||||
)
|
||||
(net "Net-(J1-Pad3)"
|
||||
(pins R9-1 R8-1 R7-1 J1-3)
|
||||
)
|
||||
(net "Net-(J1-Pad1)"
|
||||
(pins R1-1 R2-1 R3-1 J1-1)
|
||||
)
|
||||
(net "Net-(J2-Pin_1)"
|
||||
(pins R6-2 J2-1)
|
||||
)
|
||||
(net "Net-(J2-Pin_2)"
|
||||
(pins R5-2 J2-2)
|
||||
)
|
||||
(net "Net-(J2-Pin_3)"
|
||||
(pins R4-2 J2-3)
|
||||
)
|
||||
(net "Net-(J2-Pin_4)"
|
||||
(pins R3-2 J2-4)
|
||||
)
|
||||
(net "Net-(J2-Pin_5)"
|
||||
(pins R2-2 J2-5)
|
||||
)
|
||||
(net "Net-(J2-Pin_6)"
|
||||
(pins R1-2 J2-6)
|
||||
)
|
||||
(net "Net-(J1-Pad13)"
|
||||
(pins R10-1 J1-13)
|
||||
)
|
||||
(net "Net-(J1-Pad14)"
|
||||
(pins R11-1 J1-14)
|
||||
)
|
||||
(net "Net-(J3-Pin_6)"
|
||||
(pins R7-2 J3-6)
|
||||
)
|
||||
(net "Net-(J3-Pin_5)"
|
||||
(pins R8-2 J3-5)
|
||||
)
|
||||
(net "Net-(J3-Pin_4)"
|
||||
(pins R9-2 J3-4)
|
||||
)
|
||||
(net "Net-(J3-Pin_3)"
|
||||
(pins R10-2 J3-3)
|
||||
)
|
||||
(net "Net-(J3-Pin_2)"
|
||||
(pins R11-2 J3-2)
|
||||
)
|
||||
(class kicad_default "Net-(J1-Pad1)" "Net-(J1-Pad13)" "Net-(J1-Pad14)"
|
||||
"Net-(J1-Pad2)" "Net-(J1-Pad3)" "Net-(J2-Pin_1)" "Net-(J2-Pin_2)" "Net-(J2-Pin_3)"
|
||||
"Net-(J2-Pin_4)" "Net-(J2-Pin_5)" "Net-(J2-Pin_6)" "Net-(J3-Pin_1)"
|
||||
"Net-(J3-Pin_2)" "Net-(J3-Pin_3)" "Net-(J3-Pin_4)" "Net-(J3-Pin_5)"
|
||||
"Net-(J3-Pin_6)" "unconnected-(J1-Pad11)" "unconnected-(J1-Pad12)" "unconnected-(J1-Pad15)"
|
||||
"unconnected-(J1-Pad4)" "unconnected-(J1-Pad9)"
|
||||
(circuit
|
||||
(use_via "Via[0-1]_600:300_um")
|
||||
)
|
||||
(rule
|
||||
(width 200)
|
||||
(clearance 200)
|
||||
)
|
||||
)
|
||||
)
|
||||
(wiring
|
||||
)
|
||||
)
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,130 @@
|
|||
{
|
||||
"board": {
|
||||
"active_layer": 0,
|
||||
"active_layer_preset": "All Layers",
|
||||
"auto_track_width": true,
|
||||
"hidden_netclasses": [],
|
||||
"hidden_nets": [],
|
||||
"high_contrast_mode": 0,
|
||||
"net_color_mode": 1,
|
||||
"opacity": {
|
||||
"images": 0.6,
|
||||
"pads": 1.0,
|
||||
"shapes": 1.0,
|
||||
"tracks": 1.0,
|
||||
"vias": 1.0,
|
||||
"zones": 0.6
|
||||
},
|
||||
"selection_filter": {
|
||||
"dimensions": true,
|
||||
"footprints": true,
|
||||
"graphics": true,
|
||||
"keepouts": true,
|
||||
"lockedItems": false,
|
||||
"otherItems": true,
|
||||
"pads": true,
|
||||
"text": true,
|
||||
"tracks": true,
|
||||
"vias": true,
|
||||
"zones": true
|
||||
},
|
||||
"visible_items": [
|
||||
"vias",
|
||||
"footprint_text",
|
||||
"footprint_anchors",
|
||||
"ratsnest",
|
||||
"grid",
|
||||
"footprints_front",
|
||||
"footprints_back",
|
||||
"footprint_values",
|
||||
"footprint_references",
|
||||
"tracks",
|
||||
"drc_errors",
|
||||
"drawing_sheet",
|
||||
"bitmaps",
|
||||
"pads",
|
||||
"zones",
|
||||
"drc_warnings",
|
||||
"locked_item_shadows",
|
||||
"conflict_shadows",
|
||||
"shapes"
|
||||
],
|
||||
"visible_layers": "ffffffff_ffffffff_ffffffff_ffffffff",
|
||||
"zone_display_mode": 0
|
||||
},
|
||||
"git": {
|
||||
"repo_type": "",
|
||||
"repo_username": "",
|
||||
"ssh_key": ""
|
||||
},
|
||||
"meta": {
|
||||
"filename": "vga_dac_breakout.kicad_prl",
|
||||
"version": 5
|
||||
},
|
||||
"net_inspector_panel": {
|
||||
"col_hidden": [
|
||||
false,
|
||||
false,
|
||||
false,
|
||||
false,
|
||||
false,
|
||||
false,
|
||||
false,
|
||||
false,
|
||||
false,
|
||||
false
|
||||
],
|
||||
"col_order": [
|
||||
0,
|
||||
1,
|
||||
2,
|
||||
3,
|
||||
4,
|
||||
5,
|
||||
6,
|
||||
7,
|
||||
8,
|
||||
9
|
||||
],
|
||||
"col_widths": [
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0
|
||||
],
|
||||
"custom_group_rules": [],
|
||||
"expanded_rows": [],
|
||||
"filter_by_net_name": true,
|
||||
"filter_by_netclass": true,
|
||||
"filter_text": "",
|
||||
"group_by_constraint": false,
|
||||
"group_by_netclass": false,
|
||||
"show_unconnected_nets": false,
|
||||
"show_zero_pad_nets": false,
|
||||
"sort_ascending": true,
|
||||
"sorting_column": 0
|
||||
},
|
||||
"open_jobsets": [],
|
||||
"project": {
|
||||
"files": []
|
||||
},
|
||||
"schematic": {
|
||||
"selection_filter": {
|
||||
"graphics": true,
|
||||
"images": true,
|
||||
"labels": true,
|
||||
"lockedItems": false,
|
||||
"otherItems": true,
|
||||
"pins": true,
|
||||
"symbols": true,
|
||||
"text": true,
|
||||
"wires": true
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,618 @@
|
|||
{
|
||||
"board": {
|
||||
"3dviewports": [],
|
||||
"design_settings": {
|
||||
"defaults": {
|
||||
"apply_defaults_to_fp_fields": false,
|
||||
"apply_defaults_to_fp_shapes": false,
|
||||
"apply_defaults_to_fp_text": false,
|
||||
"board_outline_line_width": 0.05,
|
||||
"copper_line_width": 0.2,
|
||||
"copper_text_italic": false,
|
||||
"copper_text_size_h": 1.5,
|
||||
"copper_text_size_v": 1.5,
|
||||
"copper_text_thickness": 0.3,
|
||||
"copper_text_upright": false,
|
||||
"courtyard_line_width": 0.05,
|
||||
"dimension_precision": 4,
|
||||
"dimension_units": 3,
|
||||
"dimensions": {
|
||||
"arrow_length": 1270000,
|
||||
"extension_offset": 500000,
|
||||
"keep_text_aligned": true,
|
||||
"suppress_zeroes": true,
|
||||
"text_position": 0,
|
||||
"units_format": 0
|
||||
},
|
||||
"fab_line_width": 0.1,
|
||||
"fab_text_italic": false,
|
||||
"fab_text_size_h": 1.0,
|
||||
"fab_text_size_v": 1.0,
|
||||
"fab_text_thickness": 0.15,
|
||||
"fab_text_upright": false,
|
||||
"other_line_width": 0.1,
|
||||
"other_text_italic": false,
|
||||
"other_text_size_h": 1.0,
|
||||
"other_text_size_v": 1.0,
|
||||
"other_text_thickness": 0.15,
|
||||
"other_text_upright": false,
|
||||
"pads": {
|
||||
"drill": 0.8,
|
||||
"height": 1.27,
|
||||
"width": 2.54
|
||||
},
|
||||
"silk_line_width": 0.1,
|
||||
"silk_text_italic": false,
|
||||
"silk_text_size_h": 1.0,
|
||||
"silk_text_size_v": 1.0,
|
||||
"silk_text_thickness": 0.1,
|
||||
"silk_text_upright": false,
|
||||
"zones": {
|
||||
"min_clearance": 0.5
|
||||
}
|
||||
},
|
||||
"diff_pair_dimensions": [],
|
||||
"drc_exclusions": [],
|
||||
"meta": {
|
||||
"version": 2
|
||||
},
|
||||
"rule_severities": {
|
||||
"annular_width": "error",
|
||||
"clearance": "error",
|
||||
"connection_width": "warning",
|
||||
"copper_edge_clearance": "error",
|
||||
"copper_sliver": "warning",
|
||||
"courtyards_overlap": "error",
|
||||
"creepage": "error",
|
||||
"diff_pair_gap_out_of_range": "error",
|
||||
"diff_pair_uncoupled_length_too_long": "error",
|
||||
"drill_out_of_range": "error",
|
||||
"duplicate_footprints": "warning",
|
||||
"extra_footprint": "warning",
|
||||
"footprint": "error",
|
||||
"footprint_filters_mismatch": "ignore",
|
||||
"footprint_symbol_mismatch": "warning",
|
||||
"footprint_type_mismatch": "ignore",
|
||||
"hole_clearance": "error",
|
||||
"hole_to_hole": "warning",
|
||||
"holes_co_located": "warning",
|
||||
"invalid_outline": "error",
|
||||
"isolated_copper": "warning",
|
||||
"item_on_disabled_layer": "error",
|
||||
"items_not_allowed": "error",
|
||||
"length_out_of_range": "error",
|
||||
"lib_footprint_issues": "warning",
|
||||
"lib_footprint_mismatch": "warning",
|
||||
"malformed_courtyard": "error",
|
||||
"microvia_drill_out_of_range": "error",
|
||||
"mirrored_text_on_front_layer": "warning",
|
||||
"missing_courtyard": "ignore",
|
||||
"missing_footprint": "warning",
|
||||
"net_conflict": "warning",
|
||||
"nonmirrored_text_on_back_layer": "warning",
|
||||
"npth_inside_courtyard": "ignore",
|
||||
"padstack": "warning",
|
||||
"pth_inside_courtyard": "ignore",
|
||||
"shorting_items": "error",
|
||||
"silk_edge_clearance": "warning",
|
||||
"silk_over_copper": "warning",
|
||||
"silk_overlap": "warning",
|
||||
"skew_out_of_range": "error",
|
||||
"solder_mask_bridge": "error",
|
||||
"starved_thermal": "error",
|
||||
"text_height": "warning",
|
||||
"text_on_edge_cuts": "error",
|
||||
"text_thickness": "warning",
|
||||
"through_hole_pad_without_hole": "error",
|
||||
"too_many_vias": "error",
|
||||
"track_angle": "error",
|
||||
"track_dangling": "warning",
|
||||
"track_segment_length": "error",
|
||||
"track_width": "error",
|
||||
"tracks_crossing": "error",
|
||||
"unconnected_items": "error",
|
||||
"unresolved_variable": "error",
|
||||
"via_dangling": "warning",
|
||||
"zones_intersect": "error"
|
||||
},
|
||||
"rules": {
|
||||
"max_error": 0.005,
|
||||
"min_clearance": 0.0,
|
||||
"min_connection": 0.0,
|
||||
"min_copper_edge_clearance": 0.5,
|
||||
"min_groove_width": 0.0,
|
||||
"min_hole_clearance": 0.25,
|
||||
"min_hole_to_hole": 0.25,
|
||||
"min_microvia_diameter": 0.2,
|
||||
"min_microvia_drill": 0.1,
|
||||
"min_resolved_spokes": 2,
|
||||
"min_silk_clearance": 0.0,
|
||||
"min_text_height": 0.8,
|
||||
"min_text_thickness": 0.08,
|
||||
"min_through_hole_diameter": 0.3,
|
||||
"min_track_width": 0.0,
|
||||
"min_via_annular_width": 0.1,
|
||||
"min_via_diameter": 0.5,
|
||||
"solder_mask_to_copper_clearance": 0.0,
|
||||
"use_height_for_length_calcs": true
|
||||
},
|
||||
"teardrop_options": [
|
||||
{
|
||||
"td_onpthpad": true,
|
||||
"td_onroundshapesonly": false,
|
||||
"td_onsmdpad": true,
|
||||
"td_ontrackend": false,
|
||||
"td_onvia": true
|
||||
}
|
||||
],
|
||||
"teardrop_parameters": [
|
||||
{
|
||||
"td_allow_use_two_tracks": true,
|
||||
"td_curve_segcount": 0,
|
||||
"td_height_ratio": 1.0,
|
||||
"td_length_ratio": 0.5,
|
||||
"td_maxheight": 2.0,
|
||||
"td_maxlen": 1.0,
|
||||
"td_on_pad_in_zone": false,
|
||||
"td_target_name": "td_round_shape",
|
||||
"td_width_to_size_filter_ratio": 0.9
|
||||
},
|
||||
{
|
||||
"td_allow_use_two_tracks": true,
|
||||
"td_curve_segcount": 0,
|
||||
"td_height_ratio": 1.0,
|
||||
"td_length_ratio": 0.5,
|
||||
"td_maxheight": 2.0,
|
||||
"td_maxlen": 1.0,
|
||||
"td_on_pad_in_zone": false,
|
||||
"td_target_name": "td_rect_shape",
|
||||
"td_width_to_size_filter_ratio": 0.9
|
||||
},
|
||||
{
|
||||
"td_allow_use_two_tracks": true,
|
||||
"td_curve_segcount": 0,
|
||||
"td_height_ratio": 1.0,
|
||||
"td_length_ratio": 0.5,
|
||||
"td_maxheight": 2.0,
|
||||
"td_maxlen": 1.0,
|
||||
"td_on_pad_in_zone": false,
|
||||
"td_target_name": "td_track_end",
|
||||
"td_width_to_size_filter_ratio": 0.9
|
||||
}
|
||||
],
|
||||
"track_widths": [],
|
||||
"tuning_pattern_settings": {
|
||||
"diff_pair_defaults": {
|
||||
"corner_radius_percentage": 80,
|
||||
"corner_style": 1,
|
||||
"max_amplitude": 1.0,
|
||||
"min_amplitude": 0.2,
|
||||
"single_sided": false,
|
||||
"spacing": 1.0
|
||||
},
|
||||
"diff_pair_skew_defaults": {
|
||||
"corner_radius_percentage": 80,
|
||||
"corner_style": 1,
|
||||
"max_amplitude": 1.0,
|
||||
"min_amplitude": 0.2,
|
||||
"single_sided": false,
|
||||
"spacing": 0.6
|
||||
},
|
||||
"single_track_defaults": {
|
||||
"corner_radius_percentage": 80,
|
||||
"corner_style": 1,
|
||||
"max_amplitude": 1.0,
|
||||
"min_amplitude": 0.2,
|
||||
"single_sided": false,
|
||||
"spacing": 0.6
|
||||
}
|
||||
},
|
||||
"via_dimensions": [],
|
||||
"zones_allow_external_fillets": false
|
||||
},
|
||||
"ipc2581": {
|
||||
"dist": "",
|
||||
"distpn": "",
|
||||
"internal_id": "",
|
||||
"mfg": "",
|
||||
"mpn": ""
|
||||
},
|
||||
"layer_pairs": [],
|
||||
"layer_presets": [],
|
||||
"viewports": []
|
||||
},
|
||||
"boards": [],
|
||||
"cvpcb": {
|
||||
"equivalence_files": []
|
||||
},
|
||||
"erc": {
|
||||
"erc_exclusions": [],
|
||||
"meta": {
|
||||
"version": 0
|
||||
},
|
||||
"pin_map": [
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
2,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
1,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
1,
|
||||
2,
|
||||
1,
|
||||
1,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
0,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
2,
|
||||
1,
|
||||
2,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
2,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
2,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
2,
|
||||
1,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
2,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2
|
||||
]
|
||||
],
|
||||
"rule_severities": {
|
||||
"bus_definition_conflict": "error",
|
||||
"bus_entry_needed": "error",
|
||||
"bus_to_bus_conflict": "error",
|
||||
"bus_to_net_conflict": "error",
|
||||
"different_unit_footprint": "error",
|
||||
"different_unit_net": "error",
|
||||
"duplicate_reference": "error",
|
||||
"duplicate_sheet_names": "error",
|
||||
"endpoint_off_grid": "warning",
|
||||
"extra_units": "error",
|
||||
"footprint_filter": "ignore",
|
||||
"footprint_link_issues": "warning",
|
||||
"four_way_junction": "ignore",
|
||||
"global_label_dangling": "warning",
|
||||
"hier_label_mismatch": "error",
|
||||
"label_dangling": "error",
|
||||
"label_multiple_wires": "warning",
|
||||
"lib_symbol_issues": "warning",
|
||||
"lib_symbol_mismatch": "warning",
|
||||
"missing_bidi_pin": "warning",
|
||||
"missing_input_pin": "warning",
|
||||
"missing_power_pin": "error",
|
||||
"missing_unit": "warning",
|
||||
"multiple_net_names": "warning",
|
||||
"net_not_bus_member": "warning",
|
||||
"no_connect_connected": "warning",
|
||||
"no_connect_dangling": "warning",
|
||||
"pin_not_connected": "error",
|
||||
"pin_not_driven": "error",
|
||||
"pin_to_pin": "warning",
|
||||
"power_pin_not_driven": "error",
|
||||
"same_local_global_label": "warning",
|
||||
"similar_label_and_power": "warning",
|
||||
"similar_labels": "warning",
|
||||
"similar_power": "warning",
|
||||
"simulation_model_issue": "ignore",
|
||||
"single_global_label": "ignore",
|
||||
"unannotated": "error",
|
||||
"unconnected_wire_endpoint": "warning",
|
||||
"unit_value_mismatch": "error",
|
||||
"unresolved_variable": "error",
|
||||
"wire_dangling": "error"
|
||||
}
|
||||
},
|
||||
"libraries": {
|
||||
"pinned_footprint_libs": [],
|
||||
"pinned_symbol_libs": []
|
||||
},
|
||||
"meta": {
|
||||
"filename": "vga_dac_breakout.kicad_pro",
|
||||
"version": 3
|
||||
},
|
||||
"net_settings": {
|
||||
"classes": [
|
||||
{
|
||||
"bus_width": 12,
|
||||
"clearance": 0.2,
|
||||
"diff_pair_gap": 0.25,
|
||||
"diff_pair_via_gap": 0.25,
|
||||
"diff_pair_width": 0.2,
|
||||
"line_style": 0,
|
||||
"microvia_diameter": 0.3,
|
||||
"microvia_drill": 0.1,
|
||||
"name": "Default",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"priority": 2147483647,
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 0.2,
|
||||
"via_diameter": 0.6,
|
||||
"via_drill": 0.3,
|
||||
"wire_width": 6
|
||||
}
|
||||
],
|
||||
"meta": {
|
||||
"version": 4
|
||||
},
|
||||
"net_colors": null,
|
||||
"netclass_assignments": null,
|
||||
"netclass_patterns": []
|
||||
},
|
||||
"pcbnew": {
|
||||
"last_paths": {
|
||||
"gencad": "",
|
||||
"idf": "",
|
||||
"netlist": "",
|
||||
"plot": "",
|
||||
"pos_files": "",
|
||||
"specctra_dsn": "vga_dac_breakout.dsn",
|
||||
"step": "",
|
||||
"svg": "",
|
||||
"vrml": ""
|
||||
},
|
||||
"page_layout_descr_file": ""
|
||||
},
|
||||
"schematic": {
|
||||
"annotate_start_num": 0,
|
||||
"bom_export_filename": "${PROJECTNAME}.csv",
|
||||
"bom_fmt_presets": [],
|
||||
"bom_fmt_settings": {
|
||||
"field_delimiter": ",",
|
||||
"keep_line_breaks": false,
|
||||
"keep_tabs": false,
|
||||
"name": "CSV",
|
||||
"ref_delimiter": ",",
|
||||
"ref_range_delimiter": "",
|
||||
"string_delimiter": "\""
|
||||
},
|
||||
"bom_presets": [],
|
||||
"bom_settings": {
|
||||
"exclude_dnp": false,
|
||||
"fields_ordered": [
|
||||
{
|
||||
"group_by": false,
|
||||
"label": "Reference",
|
||||
"name": "Reference",
|
||||
"show": true
|
||||
},
|
||||
{
|
||||
"group_by": false,
|
||||
"label": "Qty",
|
||||
"name": "${QUANTITY}",
|
||||
"show": true
|
||||
},
|
||||
{
|
||||
"group_by": true,
|
||||
"label": "Value",
|
||||
"name": "Value",
|
||||
"show": true
|
||||
},
|
||||
{
|
||||
"group_by": true,
|
||||
"label": "DNP",
|
||||
"name": "${DNP}",
|
||||
"show": true
|
||||
},
|
||||
{
|
||||
"group_by": true,
|
||||
"label": "Exclude from BOM",
|
||||
"name": "${EXCLUDE_FROM_BOM}",
|
||||
"show": true
|
||||
},
|
||||
{
|
||||
"group_by": true,
|
||||
"label": "Exclude from Board",
|
||||
"name": "${EXCLUDE_FROM_BOARD}",
|
||||
"show": true
|
||||
},
|
||||
{
|
||||
"group_by": true,
|
||||
"label": "Footprint",
|
||||
"name": "Footprint",
|
||||
"show": true
|
||||
},
|
||||
{
|
||||
"group_by": false,
|
||||
"label": "Datasheet",
|
||||
"name": "Datasheet",
|
||||
"show": true
|
||||
}
|
||||
],
|
||||
"filter_string": "",
|
||||
"group_symbols": true,
|
||||
"include_excluded_from_bom": true,
|
||||
"name": "Default Editing",
|
||||
"sort_asc": true,
|
||||
"sort_field": "Reference"
|
||||
},
|
||||
"connection_grid_size": 50.0,
|
||||
"drawing": {
|
||||
"dashed_lines_dash_length_ratio": 12.0,
|
||||
"dashed_lines_gap_length_ratio": 3.0,
|
||||
"default_line_thickness": 6.0,
|
||||
"default_text_size": 50.0,
|
||||
"field_names": [],
|
||||
"intersheets_ref_own_page": false,
|
||||
"intersheets_ref_prefix": "",
|
||||
"intersheets_ref_short": false,
|
||||
"intersheets_ref_show": false,
|
||||
"intersheets_ref_suffix": "",
|
||||
"junction_size_choice": 3,
|
||||
"label_size_ratio": 0.375,
|
||||
"operating_point_overlay_i_precision": 3,
|
||||
"operating_point_overlay_i_range": "~A",
|
||||
"operating_point_overlay_v_precision": 3,
|
||||
"operating_point_overlay_v_range": "~V",
|
||||
"overbar_offset_ratio": 1.23,
|
||||
"pin_symbol_size": 25.0,
|
||||
"text_offset_ratio": 0.15
|
||||
},
|
||||
"legacy_lib_dir": "",
|
||||
"legacy_lib_list": [],
|
||||
"meta": {
|
||||
"version": 1
|
||||
},
|
||||
"net_format_name": "",
|
||||
"page_layout_descr_file": "",
|
||||
"plot_directory": "",
|
||||
"space_save_all_events": true,
|
||||
"spice_current_sheet_as_root": false,
|
||||
"spice_external_command": "spice \"%I\"",
|
||||
"spice_model_current_sheet_as_root": true,
|
||||
"spice_save_all_currents": false,
|
||||
"spice_save_all_dissipations": false,
|
||||
"spice_save_all_voltages": false,
|
||||
"subpart_first_id": 65,
|
||||
"subpart_id_separator": 0
|
||||
},
|
||||
"sheets": [
|
||||
[
|
||||
"6653d8db-6e68-4624-904b-f630210886bb",
|
||||
"Root"
|
||||
]
|
||||
],
|
||||
"text_variables": {}
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue