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dsn: include the source files the test case was exported from

This commit is contained in:
Tomasz Cichoń 2024-02-23 04:30:00 +01:00
parent 2014be1004
commit bf7d89e7bd
3 changed files with 380 additions and 11 deletions
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22
tests/data/test.dsn
View File

@ -21,8 +21,8 @@
)
)
(boundary
(path pcb 0 60400 -50400 9600 -50400 9600 -14600 60400 -14600
60400 -50400)
(path pcb 0 63906 -50400 9600 -50400 9600 -14600 63906 -14600
63906 -50400)
)
(via "Via[0-1]_800:400_um")
(rule
@ -34,7 +34,7 @@
)
(placement
(component Connector_Pin:Pin_D1.0mm_L10.0mm
(place REF** 55000.000000 -24900.000000 front 0.000000 (PN Pin_D1.0mm_L10.0mm))
(place REF** 55400.000000 -25000.000000 front 0.000000 (PN Pin_D1.0mm_L10.0mm))
)
)
(library
@ -58,6 +58,12 @@
-300.039 1469.69 -60.399 1498.78 180.805 1489.06 417.326 1440.78
643.039 1355.18 852.097 1234.48 1039.09 1081.8 1199.16 901.113
1328.18 697.085 1422.81 475.002 1480.58 240.617 1500 0))
(outline (path signal 120 500 0 481.459 -134.898 427.21 -259.792 341.277 -365.418
230.033 -443.943 101.728 -489.542 -34.121 -498.834 -167.44 -471.13
-288.34 -408.485 -387.856 -315.544 -458.606 -199.201 -495.343 -68.083
-495.343 68.083 -458.606 199.201 -387.856 315.544 -288.34 408.485
-167.44 471.13 -34.121 498.834 101.728 489.542 230.033 443.943
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(outline (path signal 120 1000 0 980.785 -195.09 923.88 -382.683 831.47 -555.57
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0 -1000 -195.09 -980.785 -382.683 -923.88 -555.57 -831.47
@ -66,12 +72,6 @@
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382.683 923.88 555.57 831.47 707.107 707.107 831.47 555.57
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(outline (path signal 120 500 0 481.459 -134.898 427.21 -259.792 341.277 -365.418
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-495.343 68.083 -458.606 199.201 -387.856 315.544 -288.34 408.485
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(pin Round[A]Pad_2000_um 1 0 0)
)
(padstack Round[A]Pad_2000_um
@ -103,9 +103,9 @@
(wire (path F.Cu 300 60000 -50000 60000 -20000)(net 5)(type route))
(wire (path F.Cu 300 20000 -20000 20000 -50000)(net 5)(type route))
(wire (path F.Cu 300 40000 -40000 50000 -40000)(net 5)(type route))
(via "Via[0-1]_800:400_um" 47000 -35000 (net 2)(type route))
(via "Via[0-1]_800:400_um" 10000 -40000 (net 1)(type route))
(via "Via[0-1]_800:400_um" 50000 -15000 (net 1)(type route))
(via "Via[0-1]_800:400_um" 10000 -40000 (net 1)(type route))
(via "Via[0-1]_800:400_um" 47000 -35000 (net 2)(type route))
(via "Via[0-1]_800:400_um" 10000 -50000 (net 2)(type route))
(via "Via[0-1]_800:400_um" 13000 -47000 (net 3)(type route))
(via "Via[0-1]_800:400_um" 35000 -20000 (net 3)(type route))

140
tests/data/test.kicad_pcb Normal file
View File

@ -0,0 +1,140 @@
(kicad_pcb (version 20221018) (generator pcbnew)
(general
(thickness 1.6)
)
(paper "A4")
(layers
(0 "F.Cu" signal)
(31 "B.Cu" signal)
(32 "B.Adhes" user "B.Adhesive")
(33 "F.Adhes" user "F.Adhesive")
(34 "B.Paste" user)
(35 "F.Paste" user)
(36 "B.SilkS" user "B.Silkscreen")
(37 "F.SilkS" user "F.Silkscreen")
(38 "B.Mask" user)
(39 "F.Mask" user)
(40 "Dwgs.User" user "User.Drawings")
(41 "Cmts.User" user "User.Comments")
(42 "Eco1.User" user "User.Eco1")
(43 "Eco2.User" user "User.Eco2")
(44 "Edge.Cuts" user)
(45 "Margin" user)
(46 "B.CrtYd" user "B.Courtyard")
(47 "F.CrtYd" user "F.Courtyard")
(48 "B.Fab" user)
(49 "F.Fab" user)
(50 "User.1" user)
(51 "User.2" user)
(52 "User.3" user)
(53 "User.4" user)
(54 "User.5" user)
(55 "User.6" user)
(56 "User.7" user)
(57 "User.8" user)
(58 "User.9" user)
)
(setup
(pad_to_mask_clearance 0)
(pcbplotparams
(layerselection 0x00010fc_ffffffff)
(plot_on_all_layers_selection 0x0000000_00000000)
(disableapertmacros false)
(usegerberextensions false)
(usegerberattributes true)
(usegerberadvancedattributes true)
(creategerberjobfile true)
(dashed_line_dash_ratio 12.000000)
(dashed_line_gap_ratio 3.000000)
(svgprecision 4)
(plotframeref false)
(viasonmask false)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15.000000)
(dxfpolygonmode true)
(dxfimperialunits true)
(dxfusepcbnewfont true)
(psnegative false)
(psa4output false)
(plotreference true)
(plotvalue true)
(plotinvisibletext false)
(sketchpadsonfab false)
(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
(drillshape 1)
(scaleselection 1)
(outputdirectory "")
)
)
(net 0 "")
(net 1 "1")
(net 2 "2")
(net 3 "3")
(net 4 "5")
(footprint "Connector_Pin:Pin_D1.0mm_L10.0mm" (layer "F.Cu")
(tstamp 3dae47ed-6a35-44fc-8752-27d12f4ee2ea)
(at 55.4 25)
(descr "solder Pin_ diameter 1.0mm, hole diameter 1.0mm (press fit), length 10.0mm")
(tags "solder Pin_ press fit")
(attr through_hole)
(fp_text reference "REF**" (at 0 2.25) (layer "F.SilkS")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp 9a52d130-31f9-4c20-8f6f-1342bd0e3fed)
)
(fp_text value "Pin_D1.0mm_L10.0mm" (at 0 -2.05) (layer "F.Fab")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp e14cc6f2-640b-46c9-852a-d8bf1fd6d77a)
)
(fp_text user "${REFERENCE}" (at 0 2.25) (layer "F.Fab")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp 9c197451-1401-405c-ab2c-04fcdbe08e4d)
)
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(fp_circle (center 0 0) (end 1.5 0)
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(fp_circle (center 0 0) (end 0.5 0)
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(fp_circle (center 0 0) (end 1 0)
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(pad "1" thru_hole circle (at 0 0) (size 2 2) (drill 1) (layers "*.Cu" "*.Mask") (tstamp 7e4a0acd-6e55-481d-9aa6-ef0ef8bcea55))
(model "${KICAD6_3DMODEL_DIR}/Connector_Pin.3dshapes/Pin_D1.0mm_L10.0mm.wrl"
(offset (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(via (at 50 15) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 916e202d-f4ec-4359-be88-c8bbeca4190b))
(via (at 10 40) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp fc2367cb-4d03-4680-9782-8c98848a1d13))
(via (at 47 35) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 2) (tstamp 9503360e-a8fa-49f0-8f06-22f318290209))
(via (at 10 50) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 2) (tstamp e609ae72-beef-41ca-9c4d-ec2ffb6b2ad3))
(via (at 13 47) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 3) (tstamp 020edbfe-ef1b-4ed1-b5f4-c4c088d573fc))
(via (at 35 20) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 3) (tstamp 9849dce8-a1b5-40a6-9316-eecd9c00299d))
(segment (start 20 50) (end 60 50) (width 0.3) (layer "F.Cu") (net 4) (tstamp 0ebf4505-fbe5-4689-8230-5b18411a780f))
(segment (start 60 20) (end 40 20) (width 0.3) (layer "F.Cu") (net 4) (tstamp 1acc54cd-4010-407b-9267-7574fd5ef025))
(segment (start 40 20) (end 40 40) (width 0.3) (layer "F.Cu") (net 4) (tstamp 243ca2e9-4862-4313-992d-72441d73aadb))
(segment (start 50 40) (end 50 30) (width 0.3) (layer "F.Cu") (net 4) (tstamp 3668a09b-9dd0-4b89-ad8e-991f7165d388))
(segment (start 60 50) (end 60 20) (width 0.3) (layer "F.Cu") (net 4) (tstamp 557b4f6e-55ef-43a2-8167-c914315f7e26))
(segment (start 20 20) (end 20 50) (width 0.3) (layer "F.Cu") (net 4) (tstamp a8819bd7-39eb-457e-b3df-d5860b2794db))
(segment (start 40 40) (end 50 40) (width 0.3) (layer "F.Cu") (net 4) (tstamp bf1178cd-7ea1-4ac1-8ce7-512c05c216fd))
(via (at 20 50) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (net 4) (tstamp 055279b7-dd22-4676-8246-bc0241a39b81))
(via (at 20 20) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (net 4) (tstamp 05d3a2a8-ebfa-4f2f-a2f3-11c8922f4329))
(via (at 40 20) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (net 4) (tstamp 8488877c-df84-41da-997e-2edc125af133))
(via (at 60 50) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (net 4) (tstamp a8559629-fe0c-4943-99a8-d8148f3a9225))
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(via (at 40 40) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (net 4) (tstamp b329b36a-7771-4249-b13c-25e843f6698f))
(via (at 60 20) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (net 4) (tstamp f4bad6be-680e-4aca-ae87-b23ff9d1bd37))
(via (at 50 40) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (net 4) (tstamp fdbf13bd-af07-4e9c-9fc9-c016b7fdb265))
)

229
tests/data/test.kicad_pro Normal file
View File

@ -0,0 +1,229 @@
{
"board": {
"3dviewports": [],
"design_settings": {
"defaults": {
"board_outline_line_width": 0.049999999999999996,
"copper_line_width": 0.19999999999999998,
"copper_text_italic": false,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"copper_text_upright": false,
"courtyard_line_width": 0.049999999999999996,
"dimension_precision": 4,
"dimension_units": 3,
"dimensions": {
"arrow_length": 1270000,
"extension_offset": 500000,
"keep_text_aligned": true,
"suppress_zeroes": false,
"text_position": 0,
"units_format": 1
},
"fab_line_width": 0.09999999999999999,
"fab_text_italic": false,
"fab_text_size_h": 1.0,
"fab_text_size_v": 1.0,
"fab_text_thickness": 0.15,
"fab_text_upright": false,
"other_line_width": 0.09999999999999999,
"other_text_italic": false,
"other_text_size_h": 1.0,
"other_text_size_v": 1.0,
"other_text_thickness": 0.15,
"other_text_upright": false,
"pads": {
"drill": 0.762,
"height": 1.524,
"width": 1.524
},
"silk_line_width": 0.09999999999999999,
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"silk_text_size_h": 1.0,
"silk_text_size_v": 1.0,
"silk_text_thickness": 0.09999999999999999,
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"zones": {
"min_clearance": 0.5
}
},
"diff_pair_dimensions": [],
"drc_exclusions": [],
"meta": {
"version": 2
},
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"connection_width": "warning",
"copper_edge_clearance": "error",
"copper_sliver": "warning",
"courtyards_overlap": "error",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"footprint": "error",
"footprint_type_mismatch": "ignore",
"hole_clearance": "error",
"hole_near_hole": "error",
"invalid_outline": "error",
"isolated_copper": "warning",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"lib_footprint_issues": "warning",
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"microvia_drill_out_of_range": "error",
"missing_courtyard": "ignore",
"missing_footprint": "warning",
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"npth_inside_courtyard": "ignore",
"padstack": "warning",
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"shorting_items": "error",
"silk_edge_clearance": "warning",
"silk_over_copper": "warning",
"silk_overlap": "warning",
"skew_out_of_range": "error",
"solder_mask_bridge": "error",
"starved_thermal": "error",
"text_height": "warning",
"text_thickness": "warning",
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"too_many_vias": "error",
"track_dangling": "warning",
"track_width": "error",
"tracks_crossing": "error",
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"unresolved_variable": "error",
"via_dangling": "warning",
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"min_via_diameter": 0.5,
"solder_mask_to_copper_clearance": 0.0,
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"teardrop_options": [
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}
],
"track_widths": [],
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},
"layer_presets": [],
"viewports": []
},
"boards": [],
"cvpcb": {
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},
"libraries": {
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"pinned_symbol_libs": []
},
"meta": {
"filename": "test.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 12,
"clearance": 0.2,
"diff_pair_gap": 0.25,
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"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
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"name": "Default",
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"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.3,
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"via_drill": 0.4,
"wire_width": 6
}
],
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},
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"netclass_assignments": null,
"netclass_patterns": []
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "",
"specctra_dsn": "test.dsn",
"step": "",
"vrml": ""
},
"page_layout_descr_file": ""
},
"schematic": {
"legacy_lib_dir": "",
"legacy_lib_list": []
},
"sheets": [],
"text_variables": {}
}