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topola
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autorouter: store a net to netname map in `Board`

This commit is contained in:
Mikolaj Wielgus 2024-05-31 23:13:12 +02:00
parent 7e022aa2cf
commit 540d9707dc
3 changed files with 57 additions and 36 deletions
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10
src/autorouter/board.rs
View File

@ -19,6 +19,7 @@ pub type NodeIndex = GenericNode<PrimitiveIndex, GenericIndex<ZoneWeight>>;
pub struct Board<R: RulesTrait> { pub struct Board<R: RulesTrait> {
layout: Layout<R>, layout: Layout<R>,
node_to_pin: HashMap<NodeIndex, String>, node_to_pin: HashMap<NodeIndex, String>,
net_to_netname: HashMap<usize, String>,
} }
impl<R: RulesTrait> Board<R> { impl<R: RulesTrait> Board<R> {
@ -26,6 +27,7 @@ impl<R: RulesTrait> Board<R> {
Self { Self {
layout, layout,
node_to_pin: HashMap::new(), node_to_pin: HashMap::new(),
net_to_netname: HashMap::new(),
} }
} }
@ -108,10 +110,18 @@ impl<R: RulesTrait> Board<R> {
zone zone
} }
pub fn bename_net(&mut self, net: usize, netname: String) {
self.net_to_netname.insert(net, netname);
}
pub fn node_pin(&self, node: NodeIndex) -> Option<&String> { pub fn node_pin(&self, node: NodeIndex) -> Option<&String> {
self.node_to_pin.get(&node) self.node_to_pin.get(&node)
} }
pub fn netname(&self, net: usize) -> Option<&String> {
self.net_to_netname.get(&net)
}
pub fn layout(&self) -> &Layout<R> { pub fn layout(&self) -> &Layout<R> {
&self.layout &self.layout
} }

59
src/dsn/design.rs
View File

@ -48,25 +48,29 @@ impl DsnDesign {
let rules = DsnRules::from_pcb(&self.pcb); let rules = DsnRules::from_pcb(&self.pcb);
let mut board = Board::new(Layout::new(Drawing::new(rules))); let mut board = Board::new(Layout::new(Drawing::new(rules)));
// mapping of pin id -> net id prepared for adding pins // mapping of pin -> net prepared for adding pins
let pin_nets = HashMap::<String, usize>::from_iter( let pin_nets = HashMap::<String, usize>::from_iter(
self.pcb self.pcb
.network .network
.net_vec .net_vec
.iter() .iter()
.map(|net| { .map(|net_pin_assignments| {
// resolve the id so we don't work with strings // resolve the id so we don't work with strings
let net_id = board let net = board
.layout() .layout()
.drawing() .drawing()
.rules() .rules()
.net_ids .netname_to_net
.get(&net.name) .get(&net_pin_assignments.name)
.unwrap(); .unwrap();
// take the list of pins // take the list of pins
// and for each pin id output (pin id, net id) // and for each pin id output (pin id, net id)
net.pins.names.iter().map(|id| (id.clone(), *net_id)) net_pin_assignments
.pins
.names
.iter()
.map(|id| (id.clone(), *net))
}) })
// flatten the nested iters into a single stream of tuples // flatten the nested iters into a single stream of tuples
.flatten(), .flatten(),
@ -85,7 +89,7 @@ impl DsnDesign {
for pin in &image.pin_vec { for pin in &image.pin_vec {
let pin_name = format!("{}-{}", place.name, pin.id); let pin_name = format!("{}-{}", place.name, pin.id);
let net_id = pin_nets.get(&pin_name).unwrap(); let net = pin_nets.get(&pin_name).unwrap();
let padstack = &self let padstack = &self
.pcb .pcb
@ -112,7 +116,7 @@ impl DsnDesign {
pin.rotate.unwrap_or(0.0) as f64, pin.rotate.unwrap_or(0.0) as f64,
circle.diameter as f64 / 2.0, circle.diameter as f64 / 2.0,
layer as u64, layer as u64,
*net_id, *net,
Some(pin_name.clone()), Some(pin_name.clone()),
) )
} }
@ -134,7 +138,7 @@ impl DsnDesign {
rect.x2 as f64, rect.x2 as f64,
rect.y2 as f64, rect.y2 as f64,
layer as u64, layer as u64,
*net_id, *net,
Some(pin_name.clone()), Some(pin_name.clone()),
) )
} }
@ -154,7 +158,7 @@ impl DsnDesign {
&path.coord_vec, &path.coord_vec,
path.width as f64, path.width as f64,
layer as u64, layer as u64,
*net_id, *net,
Some(pin_name.clone()), Some(pin_name.clone()),
) )
} }
@ -174,7 +178,7 @@ impl DsnDesign {
&polygon.coord_vec, &polygon.coord_vec,
polygon.width as f64, polygon.width as f64,
layer as u64, layer as u64,
*net_id, *net,
Some(pin_name.clone()), Some(pin_name.clone()),
) )
} }
@ -185,11 +189,11 @@ impl DsnDesign {
} }
for via in &self.pcb.wiring.via_vec { for via in &self.pcb.wiring.via_vec {
let net_id = *board let net = *board
.layout() .layout()
.drawing() .drawing()
.rules() .rules()
.net_ids .netname_to_net
.get(&via.net) .get(&via.net)
.unwrap(); .unwrap();
@ -219,7 +223,7 @@ impl DsnDesign {
0.0, 0.0,
circle.diameter as f64 / 2.0, circle.diameter as f64 / 2.0,
layer as u64, layer as u64,
net_id, net,
None, None,
) )
} }
@ -241,7 +245,7 @@ impl DsnDesign {
rect.x2 as f64, rect.x2 as f64,
rect.y2 as f64, rect.y2 as f64,
layer as u64, layer as u64,
net_id, net,
None, None,
) )
} }
@ -261,7 +265,7 @@ impl DsnDesign {
&path.coord_vec, &path.coord_vec,
path.width as f64, path.width as f64,
layer as u64, layer as u64,
net_id, net,
None, None,
) )
} }
@ -281,7 +285,7 @@ impl DsnDesign {
&polygon.coord_vec, &polygon.coord_vec,
polygon.width as f64, polygon.width as f64,
layer as u64, layer as u64,
net_id, net,
None, None,
) )
} }
@ -290,18 +294,18 @@ impl DsnDesign {
} }
for wire in self.pcb.wiring.wire_vec.iter() { for wire in self.pcb.wiring.wire_vec.iter() {
let layer_id = *board let layer = *board
.layout() .layout()
.drawing() .drawing()
.rules() .rules()
.layer_ids .layername_to_layer
.get(&wire.path.layer) .get(&wire.path.layer)
.unwrap(); .unwrap();
let net_id = *board let net = *board
.layout() .layout()
.drawing() .drawing()
.rules() .rules()
.net_ids .netname_to_net
.get(&wire.net) .get(&wire.net)
.unwrap(); .unwrap();
@ -313,12 +317,19 @@ impl DsnDesign {
0.0, 0.0,
&wire.path.coord_vec, &wire.path.coord_vec,
wire.path.width as f64, wire.path.width as f64,
layer_id as u64, layer as u64,
net_id, net,
None, None,
); );
} }
// The clone here is bad, we'll have something better later on.
let netname_to_net = &board.layout().drawing().rules().netname_to_net.clone();
for (netname, net) in netname_to_net.iter() {
board.bename_net(*net, netname.to_string());
}
board board
} }
@ -332,7 +343,7 @@ impl DsnDesign {
.layout() .layout()
.drawing() .drawing()
.rules() .rules()
.layer_ids .layername_to_layer
.get(layer_name) .get(layer_name)
.unwrap(); .unwrap();

24
src/dsn/rules.rs
View File

@ -25,12 +25,12 @@ pub struct DsnRules {
// net class name -> rule // net class name -> rule
class_rules: HashMap<String, DsnRule>, class_rules: HashMap<String, DsnRule>,
// layer names -> layer IDs for Layout // layernames -> layers for Layout
pub layer_ids: HashMap<String, u64>, pub layername_to_layer: HashMap<String, u64>,
// net names -> net IDs for Layout // netnames -> nets for Layout
pub net_ids: HashMap<String, usize>, pub netname_to_net: HashMap<String, usize>,
// net ID -> net class // net -> netclass
net_id_classes: HashMap<usize, String>, net_to_netclass: HashMap<usize, String>,
} }
impl DsnRules { impl DsnRules {
@ -43,7 +43,7 @@ impl DsnRules {
); );
// keeping this as a separate iter pass because it might be moved into a different struct later? // keeping this as a separate iter pass because it might be moved into a different struct later?
let net_ids = HashMap::from_iter( let netname_to_net = HashMap::from_iter(
pcb.network pcb.network
.class_vec .class_vec
.iter() .iter()
@ -59,7 +59,7 @@ impl DsnRules {
.iter() .iter()
.inspect(|class| { .inspect(|class| {
for net in &class.net_vec { for net in &class.net_vec {
let net_id = net_ids.get(net).unwrap(); let net_id = netname_to_net.get(net).unwrap();
net_id_classes.insert(*net_id, class.name.clone()); net_id_classes.insert(*net_id, class.name.clone());
} }
}) })
@ -69,14 +69,14 @@ impl DsnRules {
Self { Self {
structure_rule: DsnRule::from_dsn(&pcb.structure.rule), structure_rule: DsnRule::from_dsn(&pcb.structure.rule),
class_rules, class_rules,
layer_ids, layername_to_layer: layer_ids,
net_ids, netname_to_net,
net_id_classes, net_to_netclass: net_id_classes,
} }
} }
pub fn get_rule(&self, net: usize) -> &DsnRule { pub fn get_rule(&self, net: usize) -> &DsnRule {
if let Some(netclass) = self.net_id_classes.get(&net) { if let Some(netclass) = self.net_to_netclass.get(&net) {
self.class_rules self.class_rules
.get(netclass) .get(netclass)
.unwrap_or(&self.structure_rule) .unwrap_or(&self.structure_rule)