mirror of https://codeberg.org/topola/topola.git
unittests: initial simple non-rectangle routing test
This commit is contained in:
parent
6664d28af3
commit
422d1fe65c
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@ -174,10 +174,13 @@ pub fn assert_single_layer_groundless_autoroute(
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if let Some(netname) = autorouter.board().layout().rules().net_netname(net) {
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// We don't route ground.
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let mut org = unionfind.find(origin_dot.petgraph_index());
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let mut desc = unionfind.find(destination_dot.petgraph_index());
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if netname != "GND" {
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assert_eq!(
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unionfind.find(origin_dot.petgraph_index()),
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unionfind.find(destination_dot.petgraph_index())
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org,
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desc
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);
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}
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}
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@ -99,3 +99,22 @@ fn test_tht_3pin_xlr_to_tht_3pin_xlr() {
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// FIXME: The routing result is pretty bad.
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common::assert_single_layer_groundless_autoroute(&mut autorouter, "F.Cu");
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}
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#[test]
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fn test_smd_non_rectangular_buck_converter() {
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let mut path = "tests/single_layer/smd_non_rectangular_buck_converter/smd_non_rectangular_buck_converter.dsn";
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let mut autorouter = common::load_design(&path);
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let mut invoker = common::create_invoker_and_assert(autorouter);
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common::replay_and_assert(
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&mut invoker,
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"tests/single_layer/smd_non_rectangular_buck_converter/route_all.cmd",
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);
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let (mut autorouter, ..) = invoker.dissolve();
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common::assert_single_layer_groundless_autoroute(&mut autorouter, "F.Cu");
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//common::assert_number_of_conncomps(&mut autorouter, 16);
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}
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@ -0,0 +1,51 @@
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{
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"done": [
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{
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"Autoroute": [
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[
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{
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"pin": "L1-2",
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"layer": "F.Cu"
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},
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{
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"pin": "L1-1",
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"layer": "F.Cu"
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},
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{
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"pin": "D1-1",
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"layer": "F.Cu"
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},
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{
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"pin": "D1-2",
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"layer": "F.Cu"
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},
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{
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"pin": "C1-2",
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"layer": "F.Cu"
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},
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{
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"pin": "R1-1",
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"layer": "F.Cu"
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},
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{
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"pin": "C1-1",
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"layer": "F.Cu"
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},
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{
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"pin": "R1-2",
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"layer": "F.Cu"
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}
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],
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{
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"presort_by_pairwise_detours": false,
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"router_options": {
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"routed_band_width": 100.0,
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"wrap_around_bands": true,
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"squeeze_through_under_bands": true
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}
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}
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]
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}
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],
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"undone": []
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}
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@ -0,0 +1,181 @@
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(pcb /media/Projects/Projects/rust/topola/tests/single_layer/smd_non_rectangular_buck_converter/smd_non_rectangular_buck_converter.dsn
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(parser
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(string_quote ")
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(space_in_quoted_tokens on)
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(host_cad "KiCad's Pcbnew")
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(host_version "8.0.6+dfsg-1")
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)
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(resolution um 10)
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(unit um)
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(structure
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(layer F.Cu
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(type signal)
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(property
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(index 0)
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)
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)
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(layer B.Cu
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(type signal)
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(property
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(index 1)
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)
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)
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(boundary
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(path pcb 0 152000 -114000 127500 -114000 127500 -97000 152000 -97000
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152000 -114000)
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)
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(via "Via[0-1]_600:300_um")
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(rule
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(width 200)
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(clearance 200)
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(clearance 200 (type default_smd))
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(clearance 50 (type smd_smd))
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)
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)
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(placement
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(component Capacitor_SMD:C_0805_2012Metric_Pad1.18x1.45mm_HandSolder
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(place C1 134500.000000 -110462.500000 front -90.000000 (PN C))
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)
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(component Diode_SMD:D_1210_3225Metric_Pad1.42x2.65mm_HandSolder
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(place D1 138487.500000 -110000.000000 front -90.000000 (PN D))
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)
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(component Inductor_SMD:L_Coilcraft_LPS5030
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(place L1 138500.000000 -103227.500000 front 90.000000 (PN L))
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)
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(component Resistor_SMD:R_1218_3246Metric_Pad1.22x4.75mm_HandSolder
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(place R1 144000.000000 -109937.500000 front -90.000000 (PN R))
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)
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)
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(library
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(image Capacitor_SMD:C_0805_2012Metric_Pad1.18x1.45mm_HandSolder
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(outline (path signal 120 -261.252 735 261.252 735))
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(outline (path signal 120 -261.252 -735 261.252 -735))
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(outline (path signal 50 -1880 980 1880 980))
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(outline (path signal 50 -1880 -980 -1880 980))
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(outline (path signal 50 1880 980 1880 -980))
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(outline (path signal 50 1880 -980 -1880 -980))
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(outline (path signal 100 -1000 625 1000 625))
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(outline (path signal 100 -1000 -625 -1000 625))
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(outline (path signal 100 1000 625 1000 -625))
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(outline (path signal 100 1000 -625 -1000 -625))
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(pin RoundRect[T]Pad_1175x1450_250.951_um_0.000000_0 1 -1037.5 0)
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(pin RoundRect[T]Pad_1175x1450_250.951_um_0.000000_0 2 1037.5 0)
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)
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(image Diode_SMD:D_1210_3225Metric_Pad1.42x2.65mm_HandSolder
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(outline (path signal 120 -2460 1585 -2460 -1585))
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(outline (path signal 120 -2460 -1585 1600 -1585))
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(outline (path signal 120 1600 1585 -2460 1585))
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(outline (path signal 50 -2450 1580 2450 1580))
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(outline (path signal 50 -2450 -1580 -2450 1580))
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(outline (path signal 50 2450 1580 2450 -1580))
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(outline (path signal 50 2450 -1580 -2450 -1580))
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(outline (path signal 100 -1600 625 -1600 -1250))
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(outline (path signal 100 -1600 -1250 1600 -1250))
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(outline (path signal 100 -975 1250 -1600 625))
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(outline (path signal 100 1600 1250 -975 1250))
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(outline (path signal 100 1600 -1250 1600 1250))
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(pin RoundRect[T]Pad_1425x2650_250.952_um_0.000000_0 1 -1487.5 0)
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(pin RoundRect[T]Pad_1425x2650_250.952_um_0.000000_0 2 1487.5 0)
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)
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(image Inductor_SMD:L_Coilcraft_LPS5030
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(outline (path signal 120 -500 -2510 500 -2510))
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(outline (path signal 120 -500 2510 500 2510))
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(outline (path signal 50 3010 -1800 1800 -3010))
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(outline (path signal 50 3010 1800 3010 -1800))
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(outline (path signal 50 1800 -3010 -1800 -3010))
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(outline (path signal 50 1800 3010 3010 1800))
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(outline (path signal 50 -1800 -3010 -3010 -1800))
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(outline (path signal 50 -1800 3010 1800 3010))
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(outline (path signal 50 -3010 -1800 -3010 1800))
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(outline (path signal 50 -3010 1800 -1800 3010))
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(outline (path signal 100 2400 -1400 1400 -2400))
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(outline (path signal 100 2400 1400 2400 -1400))
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(outline (path signal 100 1400 -2400 -1400 -2400))
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(outline (path signal 100 1400 2400 2400 1400))
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(outline (path signal 100 -1400 2400 1400 2400))
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(outline (path signal 100 -2400 -1400 -1400 -2400))
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(outline (path signal 100 -2400 -1400 -2400 1400))
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(outline (path signal 100 -2400 1400 -1400 2400))
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(pin Cust[T]Pad_1055x3400_5510x_1995_7_um_86DF55DEC03B52FC2FEEC0D56D7CCG6E 1 -2227.5 0)
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(pin Cust[T]Pad_1055x3400_5510x_1995_7_um_319E1B03C7E38G85D4418E5F1449F697 2 2227.5 0)
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)
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(image Resistor_SMD:R_1218_3246Metric_Pad1.22x4.75mm_HandSolder
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(outline (path signal 120 -777.064 -2410 777.064 -2410))
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(outline (path signal 120 -777.064 2410 777.064 2410))
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(outline (path signal 50 -2420 -2620 -2420 2620))
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(outline (path signal 50 2420 -2620 -2420 -2620))
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(outline (path signal 50 -2420 2620 2420 2620))
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(outline (path signal 50 2420 2620 2420 -2620))
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(outline (path signal 100 -1600 -2300 -1600 2300))
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(outline (path signal 100 1600 -2300 -1600 -2300))
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(outline (path signal 100 -1600 2300 1600 2300))
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(outline (path signal 100 1600 2300 1600 -2300))
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(pin RoundRect[T]Pad_1225x4750_250.951_um_0.000000_0 1 -1562.5 0)
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(pin RoundRect[T]Pad_1225x4750_250.951_um_0.000000_0 2 1562.5 0)
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)
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(padstack Cust[T]Pad_1055x3400_5510x_1995_7_um_319E1B03C7E38G85D4418E5F1449F697
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(shape (polygon F.Cu 0 -1467.5 2755 -527.5 2755 527.5 1700 527.5 -1700 -527.5 -2755
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-1467.5 -2755 -1467.5 2755))
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(attach off)
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)
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(padstack Cust[T]Pad_1055x3400_5510x_1995_7_um_86DF55DEC03B52FC2FEEC0D56D7CCG6E
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(shape (polygon F.Cu 0 -527.5 1700 527.5 2755 1467.5 2755 1467.5 -2755 527.5 -2755
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-527.5 -1700 -527.5 1700))
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(attach off)
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)
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(padstack RoundRect[T]Pad_1175x1450_250.951_um_0.000000_0
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(shape (polygon F.Cu 0 -588.451 475 -569.348 571.035 -514.949 652.449 -433.535 706.848
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-337.499 725.95 337.5 725.951 433.535 706.848 514.949 652.449
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569.348 571.035 588.45 474.999 588.451 -475 569.348 -571.035
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514.949 -652.449 433.535 -706.848 337.499 -725.95 -337.5 -725.951
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-433.535 -706.848 -514.949 -652.449 -569.348 -571.035 -588.45 -474.999
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-588.451 475))
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(attach off)
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)
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(padstack RoundRect[T]Pad_1225x4750_250.951_um_0.000000_0
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(shape (polygon F.Cu 0 -613.451 2125 -594.348 2221.03 -539.949 2302.45 -458.535 2356.85
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||||
-362.499 2375.95 362.5 2375.95 458.535 2356.85 539.949 2302.45
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||||
594.348 2221.03 613.45 2125 613.451 -2125 594.348 -2221.03
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||||
539.949 -2302.45 458.535 -2356.85 362.499 -2375.95 -362.5 -2375.95
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-458.535 -2356.85 -539.949 -2302.45 -594.348 -2221.03 -613.45 -2125
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-613.451 2125))
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(attach off)
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)
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(padstack RoundRect[T]Pad_1425x2650_250.952_um_0.000000_0
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(shape (polygon F.Cu 0 -713.451 1075 -694.348 1171.03 -639.949 1252.45 -558.534 1306.85
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-462.499 1325.95 462.499 1325.95 558.534 1306.85 639.949 1252.45
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694.348 1171.03 713.451 1075 713.451 -1075 694.348 -1171.03
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639.949 -1252.45 558.534 -1306.85 462.499 -1325.95 -462.499 -1325.95
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-558.534 -1306.85 -639.949 -1252.45 -694.348 -1171.03 -713.451 -1075
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-713.451 1075))
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(attach off)
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)
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(padstack "Via[0-1]_600:300_um"
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(shape (circle F.Cu 600))
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(shape (circle B.Cu 600))
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(attach off)
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)
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)
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(network
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(net +3.3V
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(pins C1-1 L1-2 R1-1)
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)
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(net GND
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(pins C1-2 D1-2 R1-2)
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)
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(net "Net-(D1-K)"
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(pins D1-1 L1-1)
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)
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(class kicad_default "" +3.3V GND "Net-(D1-K)"
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(circuit
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(use_via Via[0-1]_600:300_um)
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)
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(rule
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(width 200)
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(clearance 200)
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)
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)
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)
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(wiring
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)
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)
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,83 @@
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{
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"board": {
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"active_layer": 0,
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"active_layer_preset": "All Layers",
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"auto_track_width": true,
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"hidden_netclasses": [],
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"hidden_nets": [],
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"high_contrast_mode": 0,
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"net_color_mode": 1,
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"opacity": {
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"images": 0.6,
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"pads": 1.0,
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"tracks": 1.0,
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"vias": 1.0,
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"zones": 0.6
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},
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"selection_filter": {
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"dimensions": true,
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"footprints": true,
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"graphics": true,
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"keepouts": true,
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"lockedItems": false,
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"otherItems": true,
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"pads": true,
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"text": true,
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"tracks": true,
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"vias": true,
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"zones": true
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},
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"visible_items": [
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0,
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1,
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2,
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3,
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4,
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5,
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8,
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9,
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10,
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11,
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12,
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13,
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15,
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16,
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17,
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18,
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19,
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20,
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21,
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22,
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23,
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24,
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25,
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26,
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27,
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28,
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29,
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30,
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32,
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33,
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34,
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35,
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36,
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39,
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40
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],
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"visible_layers": "fffffff_ffffffff",
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||||
"zone_display_mode": 0
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||||
},
|
||||
"git": {
|
||||
"repo_password": "",
|
||||
"repo_type": "",
|
||||
"repo_username": "",
|
||||
"ssh_key": ""
|
||||
},
|
||||
"meta": {
|
||||
"filename": "smd_non_rectangular_buck_converter.kicad_prl",
|
||||
"version": 3
|
||||
},
|
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"project": {
|
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"files": []
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}
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}
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|
@ -0,0 +1,584 @@
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{
|
||||
"board": {
|
||||
"3dviewports": [],
|
||||
"design_settings": {
|
||||
"defaults": {
|
||||
"apply_defaults_to_fp_fields": false,
|
||||
"apply_defaults_to_fp_shapes": false,
|
||||
"apply_defaults_to_fp_text": false,
|
||||
"board_outline_line_width": 0.05,
|
||||
"copper_line_width": 0.2,
|
||||
"copper_text_italic": false,
|
||||
"copper_text_size_h": 1.5,
|
||||
"copper_text_size_v": 1.5,
|
||||
"copper_text_thickness": 0.3,
|
||||
"copper_text_upright": false,
|
||||
"courtyard_line_width": 0.05,
|
||||
"dimension_precision": 4,
|
||||
"dimension_units": 3,
|
||||
"dimensions": {
|
||||
"arrow_length": 1270000,
|
||||
"extension_offset": 500000,
|
||||
"keep_text_aligned": true,
|
||||
"suppress_zeroes": false,
|
||||
"text_position": 0,
|
||||
"units_format": 1
|
||||
},
|
||||
"fab_line_width": 0.1,
|
||||
"fab_text_italic": false,
|
||||
"fab_text_size_h": 1.0,
|
||||
"fab_text_size_v": 1.0,
|
||||
"fab_text_thickness": 0.15,
|
||||
"fab_text_upright": false,
|
||||
"other_line_width": 0.1,
|
||||
"other_text_italic": false,
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||||
"other_text_size_h": 1.0,
|
||||
"other_text_size_v": 1.0,
|
||||
"other_text_thickness": 0.15,
|
||||
"other_text_upright": false,
|
||||
"pads": {
|
||||
"drill": 0.762,
|
||||
"height": 1.524,
|
||||
"width": 1.524
|
||||
},
|
||||
"silk_line_width": 0.1,
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||||
"silk_text_italic": false,
|
||||
"silk_text_size_h": 1.0,
|
||||
"silk_text_size_v": 1.0,
|
||||
"silk_text_thickness": 0.1,
|
||||
"silk_text_upright": false,
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||||
"zones": {
|
||||
"min_clearance": 0.5
|
||||
}
|
||||
},
|
||||
"diff_pair_dimensions": [],
|
||||
"drc_exclusions": [],
|
||||
"meta": {
|
||||
"version": 2
|
||||
},
|
||||
"rule_severities": {
|
||||
"annular_width": "error",
|
||||
"clearance": "error",
|
||||
"connection_width": "warning",
|
||||
"copper_edge_clearance": "error",
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
{
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
{
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"text_variables": {}
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue