mirror of https://codeberg.org/topola/topola.git
tests: add export of prerouted_lm317_breakout
The file can now be parsed and partially loaded into Layout.
This commit is contained in:
Tomasz Cichoń
parent
fb6922a5e5
commit
23fe001647
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@ -251,8 +251,8 @@ fn main() -> Result<(), anyhow::Error> {
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]),
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]),
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}));*/
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}));*/
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//let design = DsnDesign::load_from_file("tests/data/prerouted_lm317_breakout/prerouted_lm317_breakout.dsn")?;
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let design = DsnDesign::load_from_file("tests/data/prerouted_lm317_breakout/prerouted_lm317_breakout.dsn")?;
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let design = DsnDesign::load_from_file("tests/data/test/test.dsn")?;
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//let design = DsnDesign::load_from_file("tests/data/test/test.dsn")?;
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//dbg!(&design);
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//dbg!(&design);
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let layout = design.make_layout();
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let layout = design.make_layout();
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let board = Board::new(layout);
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let board = Board::new(layout);
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@ -0,0 +1,583 @@
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(pcb prerouted_lm317_breakout.dsn
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(parser
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(string_quote ")
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(space_in_quoted_tokens on)
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(host_cad "KiCad's Pcbnew")
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(host_version "7.0.9")
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)
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(resolution um 10)
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(unit um)
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(structure
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(layer F.Cu
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(type signal)
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(property
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(index 0)
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)
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)
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(layer B.Cu
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(type signal)
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(property
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(index 1)
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)
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)
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(boundary
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(path pcb 0 149000 -85500 111000 -85500 111000 -71500 149000 -71500
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149000 -85500)
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)
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(plane GND (polygon F.Cu 0 111000 -71500 149000 -71500 149000 -85500 111000 -85500
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111000 -71500))
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(plane GND (polygon B.Cu 0 111000 -71500 149000 -71500 149000 -85500 111000 -85500
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111000 -71500))
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(via "Via[0-1]_800:400_um" "Via[0-1]_1800:600_um" "Via[0-1]_1200:500_um")
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(rule
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(width 250)
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(clearance 200.1)
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(clearance 200.1 (type default_smd))
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(clearance 50 (type smd_smd))
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)
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)
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(placement
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(component "Package_TO_SOT_THT:TO-220-3_Vertical"
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(place U1 132580.000000 -81182.379000 front 180.000000 (PN "LM317_TO-220"))
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)
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(component "TerminalBlock:TerminalBlock_Altech_AK300-2_P5.00mm"
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(place J2 145500.000000 -78500.000000 front 180.000000 (PN Screw_Terminal_01x02))
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(place J1 120000.000000 -78500.000000 front 180.000000 (PN Screw_Terminal_01x02))
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)
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(component Capacitor_THT:CP_Radial_D6.3mm_P2.50mm
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(place C3 133500.000000 -76500.000000 front 90.000000 (PN 470u))
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(place C2 126500.000000 -76500.000000 front 90.000000 (PN 470u))
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)
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(component Capacitor_SMD:C_1206_3216Metric
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(place C1 124500.000000 -82500.000000 back 90.000000 (PN 100n))
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(place C4 128500.000000 -83750.000000 back 0.000000 (PN 100n))
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)
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(component Resistor_SMD:R_1206_3216Metric
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(place R2 135500.000000 -79962.500000 back 270.000000 (PN 750))
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(place R1 134000.000000 -83500.000000 back 180.000000 (PN 240))
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)
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)
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(library
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(image "Package_TO_SOT_THT:TO-220-3_Vertical"
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(outline (path signal 120 -2580 3270 -2580 -1371))
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(outline (path signal 120 -2580 3270 7660 3270))
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(outline (path signal 120 -2580 1760 7660 1760))
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(outline (path signal 120 -2580 -1371 7660 -1371))
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(outline (path signal 120 690 3270 690 1760))
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(outline (path signal 120 4391 3270 4391 1760))
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(outline (path signal 120 7660 3270 7660 -1371))
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(outline (path signal 50 -2710 3400 -2710 -1510))
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(outline (path signal 50 -2710 -1510 7790 -1510))
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(outline (path signal 50 7790 3400 -2710 3400))
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(outline (path signal 50 7790 -1510 7790 3400))
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(outline (path signal 100 -2460 3150 -2460 -1250))
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(outline (path signal 100 -2460 1880 7540 1880))
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(outline (path signal 100 -2460 -1250 7540 -1250))
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(outline (path signal 100 690 3150 690 1880))
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(outline (path signal 100 4390 3150 4390 1880))
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(outline (path signal 100 7540 3150 -2460 3150))
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(outline (path signal 100 7540 -1250 7540 3150))
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(pin Rect[A]Pad_1905x2000_um 1 0 0)
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(pin Oval[A]Pad_1905x2000_um 2 2540 0)
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(pin Oval[A]Pad_1905x2000_um 3 5080 0)
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)
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(image "TerminalBlock:TerminalBlock_Altech_AK300-2_P5.00mm"
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(outline (path signal 120 -2650 6300 -2650 -6300))
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(outline (path signal 120 -2650 -6300 7700 -6300))
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(outline (path signal 120 7700 1500 8200 1200))
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(outline (path signal 120 7700 -3900 7700 1500))
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(outline (path signal 120 7700 -5350 8200 -5600))
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(outline (path signal 120 7700 -6300 7700 -5350))
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(outline (path signal 120 8200 6300 -2650 6300))
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(outline (path signal 120 8200 1200 8200 6300))
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(outline (path signal 120 8200 -3650 7700 -3900))
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(outline (path signal 120 8200 -3700 8200 -3650))
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(outline (path signal 120 8200 -5600 8200 -3700))
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(outline (path signal 50 -2830 6470 -2830 -6470))
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(outline (path signal 50 -2830 6470 8360 6470))
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(outline (path signal 50 8360 -6470 -2830 -6470))
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(outline (path signal 50 8360 -6470 8360 6470))
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(outline (path signal 100 -2580 3170 -2580 6220))
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(outline (path signal 100 -2580 3170 7610 3170))
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(outline (path signal 100 -2580 640 -2580 3170))
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(outline (path signal 100 -2580 640 -1640 640))
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(outline (path signal 100 -2580 -6220 -2580 640))
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(outline (path signal 100 -2580 -6220 -2020 -6220))
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(outline (path signal 100 -2020 3430 -2020 5970))
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(outline (path signal 100 -2020 250 -2020 -4320))
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(outline (path signal 100 -2020 250 -1640 250))
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(outline (path signal 100 -2020 -4320 -2020 -6220))
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(outline (path signal 100 -2020 -6220 2040 -6220))
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(outline (path signal 100 -1260 250 1280 250))
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(outline (path signal 100 -1260 -2540 -1260 250))
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(outline (path signal 100 -1260 -2540 1280 -2540))
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(outline (path signal 100 1280 -2540 1280 250))
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(outline (path signal 100 1660 640 3360 640))
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(outline (path signal 100 1660 250 -1640 250))
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(outline (path signal 100 1660 -510 1280 -510))
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(outline (path signal 100 1660 -3680 -1640 -3680))
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(outline (path signal 100 1660 -3680 1660 -510))
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(outline (path signal 100 2040 5970 -2020 5970))
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(outline (path signal 100 2040 3430 -2020 3430))
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(outline (path signal 100 2040 3430 2040 5970))
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(outline (path signal 100 2040 250 1660 250))
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(outline (path signal 100 2040 -4320 -2020 -4320))
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(outline (path signal 100 2040 -4320 2040 250))
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(outline (path signal 100 2040 -6220 2040 -4320))
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(outline (path signal 100 2040 -6220 2980 -6220))
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(outline (path signal 100 2980 5970 7050 5970))
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(outline (path signal 100 2980 3430 2980 5970))
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(outline (path signal 100 2980 250 3360 250))
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(outline (path signal 100 2980 -4320 2980 250))
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(outline (path signal 100 2980 -4320 7050 -4320))
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(outline (path signal 100 2980 -6220 2980 -4320))
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(outline (path signal 100 2980 -6220 7050 -6220))
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(outline (path signal 100 3360 250 6670 250))
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(outline (path signal 100 3360 -510 3740 -510))
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(outline (path signal 100 3360 -3680 3360 -510))
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(outline (path signal 100 3390 4450 6440 5080))
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(outline (path signal 100 3520 4320 6560 4950))
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(outline (path signal 100 3740 250 6280 250))
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(outline (path signal 100 3740 -2540 3740 250))
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(outline (path signal 100 3740 -2540 6280 -2540))
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(outline (path signal 100 6280 -2540 6280 250))
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(outline (path signal 100 6670 640 3360 640))
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(outline (path signal 100 6670 -510 6280 -510))
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(outline (path signal 100 6670 -3680 3360 -3680))
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(outline (path signal 100 6670 -3680 6670 -510))
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(outline (path signal 100 7050 5970 7050 3430))
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(outline (path signal 100 7050 3430 2980 3430))
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(outline (path signal 100 7050 250 6670 250))
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(outline (path signal 100 7050 250 7050 -4320))
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(outline (path signal 100 7050 -4320 7050 -6220))
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(outline (path signal 100 7050 -6220 7610 -6220))
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(outline (path signal 100 7610 6220 -2580 6220))
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(outline (path signal 100 7610 6220 7610 3170))
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||||||
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(outline (path signal 100 7610 6220 8110 6220))
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||||||
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(outline (path signal 100 7610 3170 7610 1650))
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||||||
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(outline (path signal 100 7610 1650 7610 640))
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||||||
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(outline (path signal 100 7610 640 6670 640))
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||||||
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(outline (path signal 100 7610 640 7610 -4060))
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||||||
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(outline (path signal 100 7610 -4060 7610 -5210))
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||||||
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(outline (path signal 100 7610 -5210 7610 -6220))
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||||||
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(outline (path signal 100 8110 6220 8110 1400))
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||||||
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(outline (path signal 100 8110 1400 7610 1650))
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||||||
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(outline (path signal 100 8110 -3810 7610 -4060))
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||||||
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(outline (path signal 100 8110 -3810 8110 -5460))
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(outline (path signal 100 8110 -5460 7610 -5210))
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(outline (path signal 0 1635.36 2455.36 1650 2420 1637.54 2389.92 1639.02 2388.74
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1635.4 2384.76 1635.36 2384.65 1635.27 2384.61 1461.93 2193.95
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1262 2022.69 1042.32 1877.62 806.305 1760.99 557.622 1674.61
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300.129 1619.83 37.822 1597.49 -225.227 1607.94 -484.935 1651.01
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-737.272 1726.05 -978.32 1831.88 -1204.34 1966.86 -1411.82 2128.89
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-1595.1 2313.02 -1595.33 2313.11 -1595.43 2313.35 -1597.54 2315.47
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-1596.64 2316.26 -1609.98 2348.47 -1595.33 2383.82 -1559.98 2398.47
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-1524.62 2383.82 -1523.32 2380.67 -1522.41 2381.47 -1330.97 2190.98
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-1115.76 2027.83 -880.645 1894.96 -629.861 1794.76 -367.922 1729.02
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-99.54 1698.94 170.453 1705.05 437.198 1747.25 695.895 1824.77
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941.887 1936.22 1170.75 2079.59 1378.36 2252.31 1560.98 2451.27
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1562.46 2450.08 1564.64 2455.36 1600 2470))
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(outline (path signal 0 -817.346 5210.62 -815.644 5213.67 -696.695 5128.32 -600.041 5018.36
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-530.658 4889.44 -492.114 4748.2 -486.393 4601.91 -513.79 4458.1
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-572.895 4324.15 -660.666 4206.98 -661.08 4207.37 -661.671 4205.95
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-697.026 4191.3 -732.381 4205.95 -747.026 4241.3 -732.971 4275.23
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-733.385 4275.62 -659.214 4374.64 -609.267 4487.83 -586.115 4609.36
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-590.949 4732.99 -623.521 4852.34 -682.154 4961.28 -763.832 5054.21
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-864.351 5126.33 -862.649 5129.38 -875.353 5134.65 -889.998 5170
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-875.353 5205.35 -839.998 5220))
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(outline (path signal 0 609.736 5129.35 624.381 5093.99 609.736 5058.64 607.267 5057.62
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607.911 5056.9 514.147 4950.63 446.538 4826.07 408.51 4689.55
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401.992 4547.98 427.315 4408.53 483.194 4278.29 566.796 4163.85
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566.203 4163.31 580 4130 565.355 4094.64 530 4080 494.645 4094.64
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493.796 4096.69 493.203 4096.15 406.758 4211.04 344.529 4340.66
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308.936 4479.96 301.36 4623.55 322.096 4765.82 370.339 4901.27
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444.214 5024.62 538.817 5128.85 539.026 5129.35 539.423 5129.51
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540.85 5131.09 541.494 5130.37 574.381 5143.99))
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(outline (path signal 0 241.258 8555.41 536.982 8515.93 825.869 8441.4 1103.78 8332.88
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1366.73 8191.92 1610.95 8020.55 1609.73 8019.03 1615.18 8016.77
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1629.83 7981.42 1615.18 7946.06 1579.83 7931.42 1549.92 7943.81
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1548.71 7942.28 1314.29 8106.77 1061.89 8242.07 795.136 8346.24
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517.842 8417.78 233.985 8455.67 -52.366 8459.37 -337.106 8428.81
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-616.154 8364.45 -885.511 8267.2 -1141.32 8138.46 -1379.9 7980.07
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-1381.28 7981.9 -1410 7970 -1445.36 7984.65 -1460 8020 -1445.36 8055.35
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-1438.72 8058.1 -1440.1 8059.93 -1191.54 8224.94 -925.039 8359.06
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-644.422 8460.37 -353.707 8527.43 -57.063 8559.26))
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(outline (path signal 0 6625.35 2455.36 6640 2420 6627.48 2389.78 6628.93 2388.62
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6625.41 2384.77 6625.35 2384.64 6625.25 2384.6 6451.9 2195.08
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6252.18 2025.06 6032.88 1881.19 5797.38 1765.71 5549.36 1680.41
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5292.65 1626.61 5031.24 1605.14 4769.2 1616.35 4510.58 1660.05
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4259.4 1735.58 4019.56 1841.74 3794.79 1976.91 3588.57 2138.98
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3406.63 2322.86 3406.41 2322.96 3406.31 2323.19 3404.09 2325.43
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3405.04 2326.26 3391.76 2358.31 3406.41 2393.67 3441.76 2408.31
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3477.12 2393.67 3478.48 2390.37 3479.43 2391.2 3669.55 2200.87
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3883.43 2037.7 4117.23 1904.63 4366.74 1804.06 4627.46 1737.78
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4894.71 1707 5163.68 1712.27 5429.52 1753.5 5687.44 1829.93
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5932.82 1940.21 6161.23 2082.33 6368.56 2253.75 6551.08 2451.38
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6552.52 2450.22 6554.65 2455.36 6590 2470))
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(outline (path signal 0 4182.65 5210.62 4184.35 5213.67 4303.3 5128.32 4399.96 5018.36
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4469.34 4889.44 4507.88 4748.2 4513.6 4601.91 4486.21 4458.1
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4427.1 4324.15 4339.33 4206.98 4338.92 4207.37 4338.33 4205.95
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4302.97 4191.3 4267.62 4205.95 4252.97 4241.3 4267.03 4275.23
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4266.61 4275.62 4340.78 4374.64 4390.73 4487.83 4413.88 4609.36
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4409.05 4732.99 4376.48 4852.34 4317.84 4961.28 4236.17 5054.21
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4135.65 5126.33 4137.35 5129.38 4124.65 5134.65 4110 5170
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4124.65 5205.35 4160 5220))
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(outline (path signal 0 5258.95 8548.81 5553.83 8508.47 5841.77 8433.17 6118.66 8324
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6380.51 8182.52 6623.58 8010.77 6622.39 8009.29 6627.69 8007.09
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6642.33 7971.74 6627.69 7936.38 6592.33 7921.74 6562.27 7934.19
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6561.09 7932.7 6327.8 8097.55 6076.48 8233.33 5810.73 8338.11
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5534.37 8410.38 5251.35 8449.1 4965.73 8453.72 4681.61 8424.18
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4403.05 8360.89 4134.05 8264.77 3878.47 8137.19 3639.97 7979.98
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3638.57 7981.84 3610 7970 3574.64 7984.65 3560 8020 3574.64 8055.35
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3581.43 8058.16 3580.03 8060.02 3828.53 8223.82 4094.83 8356.75
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4375.1 8456.9 4665.33 8522.84 4961.36 8553.63))
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||||||
|
-408.535 -856.848 -489.949 -802.449 -544.348 -721.035 -563.45 -624.999
|
||||||
|
-563.451 625))
|
||||||
|
(attach off)
|
||||||
|
)
|
||||||
|
(padstack RoundRect[T]Pad_1150x1800_250.951_um_0.000000_0
|
||||||
|
(shape (polygon F.Cu 0 -575.951 650 -556.848 746.035 -502.449 827.449 -421.035 881.848
|
||||||
|
-324.999 900.95 325 900.951 421.035 881.848 502.449 827.449
|
||||||
|
556.848 746.035 575.95 649.999 575.951 -650 556.848 -746.035
|
||||||
|
502.449 -827.449 421.035 -881.848 324.999 -900.95 -325 -900.951
|
||||||
|
-421.035 -881.848 -502.449 -827.449 -556.848 -746.035 -575.95 -649.999
|
||||||
|
-575.951 650))
|
||||||
|
(attach off)
|
||||||
|
)
|
||||||
|
(padstack Rect[A]Pad_1600x1600_um
|
||||||
|
(shape (rect F.Cu -800 -800 800 800))
|
||||||
|
(shape (rect B.Cu -800 -800 800 800))
|
||||||
|
(attach off)
|
||||||
|
)
|
||||||
|
(padstack Rect[A]Pad_1905x2000_um
|
||||||
|
(shape (rect F.Cu -952.5 -1000 952.5 1000))
|
||||||
|
(shape (rect B.Cu -952.5 -1000 952.5 1000))
|
||||||
|
(attach off)
|
||||||
|
)
|
||||||
|
(padstack Rect[A]Pad_1980x3960_um
|
||||||
|
(shape (rect F.Cu -990 -1980 990 1980))
|
||||||
|
(shape (rect B.Cu -990 -1980 990 1980))
|
||||||
|
(attach off)
|
||||||
|
)
|
||||||
|
(padstack "Via[0-1]_800:400_um"
|
||||||
|
(shape (circle F.Cu 800))
|
||||||
|
(shape (circle B.Cu 800))
|
||||||
|
(attach off)
|
||||||
|
)
|
||||||
|
(padstack "Via[0-1]_1800:600_um"
|
||||||
|
(shape (circle F.Cu 1800))
|
||||||
|
(shape (circle B.Cu 1800))
|
||||||
|
(attach off)
|
||||||
|
)
|
||||||
|
(padstack "Via[0-1]_1200:500_um"
|
||||||
|
(shape (circle F.Cu 1200))
|
||||||
|
(shape (circle B.Cu 1200))
|
||||||
|
(attach off)
|
||||||
|
)
|
||||||
|
)
|
||||||
|
(network
|
||||||
|
(net GND
|
||||||
|
(pins J2-1 J1-2 C3-2 C2-2 C1-2 R2-2 C4-2)
|
||||||
|
)
|
||||||
|
(net /adj
|
||||||
|
(pins U1-1 R2-1 R1-2)
|
||||||
|
)
|
||||||
|
(net /wejście
|
||||||
|
(pins U1-3 J1-1 C2-1 C1-1)
|
||||||
|
)
|
||||||
|
(net /wyjście
|
||||||
|
(pins U1-2 J2-2 C3-1 R1-1 C4-1)
|
||||||
|
)
|
||||||
|
(class kicad_default "" /adj GND
|
||||||
|
(circuit
|
||||||
|
(use_via Via[0-1]_800:400_um)
|
||||||
|
)
|
||||||
|
(rule
|
||||||
|
(width 250)
|
||||||
|
(clearance 200.1)
|
||||||
|
)
|
||||||
|
)
|
||||||
|
(class Wejście /wejście
|
||||||
|
(circuit
|
||||||
|
(use_via Via[0-1]_1800:600_um)
|
||||||
|
)
|
||||||
|
(rule
|
||||||
|
(width 1200)
|
||||||
|
(clearance 400.1)
|
||||||
|
)
|
||||||
|
)
|
||||||
|
(class Wyjście /wyjście
|
||||||
|
(circuit
|
||||||
|
(use_via Via[0-1]_1200:500_um)
|
||||||
|
)
|
||||||
|
(rule
|
||||||
|
(width 1000)
|
||||||
|
(clearance 300.1)
|
||||||
|
)
|
||||||
|
)
|
||||||
|
)
|
||||||
|
(wiring
|
||||||
|
(wire (path B.Cu 250 135462 -83500 135462 -81462.5 135500 -81425)(net /adj)(type route))
|
||||||
|
(wire (path B.Cu 250 132580 -81182.4 135257 -81182.4 135500 -81425)(net /adj)(type route))
|
||||||
|
(wire (path F.Cu 1200 126500 -80000 126500 -76682.4)(net /wejście)(type route))
|
||||||
|
(wire (path F.Cu 1200 124818 -78500 127500 -81182.4 127500 -81000)(net /wejście)(type route))
|
||||||
|
(wire (path F.Cu 1200 120000 -78500 124818 -78500)(net /wejście)(type route))
|
||||||
|
(wire (path F.Cu 1200 127500 -81000 126500 -80000)(net /wejście)(type route))
|
||||||
|
(wire (path B.Cu 1200 124500 -81025 127343 -81025 127500 -81182.4)(net /wejście)(type route))
|
||||||
|
(wire (path F.Cu 1000 131500 -78500 130040 -79960 133500 -76500)(net /wyjście)(type route))
|
||||||
|
(wire (path F.Cu 1000 130040 -81182.4 130040 -79960)(net /wyjście)(type route))
|
||||||
|
(wire (path F.Cu 1000 140500 -78500 131500 -78500)(net /wyjście)(type route))
|
||||||
|
(wire (path B.Cu 1000 132538 -83500 129975 -83500 129975 -81247.4 130040 -81182.4)(net /wyjście)(type route))
|
||||||
|
)
|
||||||
|
)
|
||||||
Loading…
Reference in New Issue