mirror of https://codeberg.org/topola/topola.git
test: Add 3x4_tactswitch_ir_remote test, without test routines yet as usual
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||||
(pin Round[A]Pad_1350.000000_um 4 2000 -2000)
|
||||
(pin Round[A]Pad_1350.000000_um 5 0 -4000)
|
||||
(pin Round[A]Pad_1350.000000_um 6 2000 -4000)
|
||||
)
|
||||
(image Resistor_SMD:R_0603_1608Metric_Pad0.98x0.95mm_HandSolder
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||||
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|
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|
||||
(pin RoundRect[T]Pad_975.000000x950.000000_238.404000_um_0.000000_0 2 912.5 0)
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)
|
||||
(image "Capacitor_Tantalum_SMD:CP_EIA-7343-31_Kemet-D"
|
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
)
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||||
(image "Package_QFP:TQFP-32_7x7mm_P0.8mm"
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||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
(outline (path signal 50 -3330 -3750 -3750 -3750))
|
||||
(outline (path signal 50 -3330 -5150 -3330 -3750))
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
(pin RoundRect[T]Pad_1475.000000x550.000000_138.023000_um_0.000000_0 2 -4162.5 2000)
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
(pin RoundRect[T]Pad_1475.000000x550.000000_138.023000_um_0.000000_0 7 -4162.5 -2000)
|
||||
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|
||||
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|
||||
(pin RoundRect[T]Pad_550.000000x1475.000000_138.023000_um_0.000000_0 10 -2000 -4162.5)
|
||||
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|
||||
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|
||||
(pin RoundRect[T]Pad_550.000000x1475.000000_138.023000_um_0.000000_0 13 400 -4162.5)
|
||||
(pin RoundRect[T]Pad_550.000000x1475.000000_138.023000_um_0.000000_0 14 1200 -4162.5)
|
||||
(pin RoundRect[T]Pad_550.000000x1475.000000_138.023000_um_0.000000_0 15 2000 -4162.5)
|
||||
(pin RoundRect[T]Pad_550.000000x1475.000000_138.023000_um_0.000000_0 16 2800 -4162.5)
|
||||
(pin RoundRect[T]Pad_1475.000000x550.000000_138.023000_um_0.000000_0 17 4162.5 -2800)
|
||||
(pin RoundRect[T]Pad_1475.000000x550.000000_138.023000_um_0.000000_0 18 4162.5 -2000)
|
||||
(pin RoundRect[T]Pad_1475.000000x550.000000_138.023000_um_0.000000_0 19 4162.5 -1200)
|
||||
(pin RoundRect[T]Pad_1475.000000x550.000000_138.023000_um_0.000000_0 20 4162.5 -400)
|
||||
(pin RoundRect[T]Pad_1475.000000x550.000000_138.023000_um_0.000000_0 21 4162.5 400)
|
||||
(pin RoundRect[T]Pad_1475.000000x550.000000_138.023000_um_0.000000_0 22 4162.5 1200)
|
||||
(pin RoundRect[T]Pad_1475.000000x550.000000_138.023000_um_0.000000_0 23 4162.5 2000)
|
||||
(pin RoundRect[T]Pad_1475.000000x550.000000_138.023000_um_0.000000_0 24 4162.5 2800)
|
||||
(pin RoundRect[T]Pad_550.000000x1475.000000_138.023000_um_0.000000_0 25 2800 4162.5)
|
||||
(pin RoundRect[T]Pad_550.000000x1475.000000_138.023000_um_0.000000_0 26 2000 4162.5)
|
||||
(pin RoundRect[T]Pad_550.000000x1475.000000_138.023000_um_0.000000_0 27 1200 4162.5)
|
||||
(pin RoundRect[T]Pad_550.000000x1475.000000_138.023000_um_0.000000_0 28 400 4162.5)
|
||||
(pin RoundRect[T]Pad_550.000000x1475.000000_138.023000_um_0.000000_0 29 -400 4162.5)
|
||||
(pin RoundRect[T]Pad_550.000000x1475.000000_138.023000_um_0.000000_0 30 -1200 4162.5)
|
||||
(pin RoundRect[T]Pad_550.000000x1475.000000_138.023000_um_0.000000_0 31 -2000 4162.5)
|
||||
(pin RoundRect[T]Pad_550.000000x1475.000000_138.023000_um_0.000000_0 32 -2800 4162.5)
|
||||
)
|
||||
(padstack Round[A]Pad_1350.000000_um
|
||||
(shape (circle F.Cu 1350))
|
||||
(shape (circle B.Cu 1350))
|
||||
(attach off)
|
||||
)
|
||||
(padstack Round[A]Pad_1800.000000_um
|
||||
(shape (circle F.Cu 1800))
|
||||
(shape (circle B.Cu 1800))
|
||||
(attach off)
|
||||
)
|
||||
(padstack Round[A]Pad_2000.000000_um
|
||||
(shape (circle F.Cu 2000))
|
||||
(shape (circle B.Cu 2000))
|
||||
(attach off)
|
||||
)
|
||||
(padstack RoundRect[T]Pad_2070.000000x2590.000000_250.951000_um_0.000000_0
|
||||
(shape (polygon F.Cu 0 -1035.95 1045 -1016.85 1141.04 -962.449 1222.45 -881.035 1276.85
|
||||
-784.999 1295.95 785 1295.95 881.035 1276.85 962.449 1222.45
|
||||
1016.85 1141.04 1035.95 1045 1035.95 -1045 1016.85 -1141.04
|
||||
962.449 -1222.45 881.035 -1276.85 784.999 -1295.95 -785 -1295.95
|
||||
-881.035 -1276.85 -962.449 -1222.45 -1016.85 -1141.04 -1035.95 -1045
|
||||
-1035.95 1045))
|
||||
(attach off)
|
||||
)
|
||||
(padstack RoundRect[T]Pad_550.000000x1475.000000_138.023000_um_0.000000_0
|
||||
(shape (polygon F.Cu 0 -275.523 600 -265.017 652.819 -235.097 697.597 -190.319 727.517
|
||||
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|
||||
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|
||||
235.097 -697.597 190.319 -727.517 137.499 -738.022 -137.5 -738.023
|
||||
-190.319 -727.517 -235.097 -697.597 -265.017 -652.819 -275.522 -599.999
|
||||
-275.523 600))
|
||||
(attach off)
|
||||
)
|
||||
(padstack RoundRect[T]Pad_900.000000x950.000000_225.856000_um_0.000000_0
|
||||
(shape (polygon F.Cu 0 -450.856 250 -433.664 336.431 -384.704 409.704 -311.431 458.664
|
||||
-225 475.856 225 475.856 311.431 458.664 384.704 409.704
|
||||
433.664 336.431 450.856 250 450.856 -250 433.664 -336.431
|
||||
384.704 -409.704 311.431 -458.664 225 -475.856 -225 -475.856
|
||||
-311.431 -458.664 -384.704 -409.704 -433.664 -336.431 -450.856 -250
|
||||
-450.856 250))
|
||||
(attach off)
|
||||
)
|
||||
(padstack RoundRect[T]Pad_975.000000x950.000000_238.404000_um_0.000000_0
|
||||
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|
||||
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|
||||
470.257 328.733 488.404 237.5 488.404 -237.5 470.257 -328.733
|
||||
418.577 -406.077 341.233 -457.757 250 -475.904 -250 -475.904
|
||||
-341.233 -457.757 -418.577 -406.077 -470.257 -328.733 -488.404 -237.5
|
||||
-488.404 237.5))
|
||||
(attach off)
|
||||
)
|
||||
(padstack RoundRect[T]Pad_1475.000000x550.000000_138.023000_um_0.000000_0
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
-738.023 137.5))
|
||||
(attach off)
|
||||
)
|
||||
(padstack RoundRect[T]Pad_1800.000000x1400.000000_250.950000_um_0.000000_0
|
||||
(shape (polygon F.Cu 0 -900.951 450.001 -881.849 546.035 -827.449 627.449 -746.035 681.849
|
||||
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|
||||
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|
||||
827.449 -627.449 746.035 -681.849 650.001 -700.951 -650.001 -700.951
|
||||
-746.035 -681.849 -827.449 -627.449 -881.849 -546.035 -900.951 -450.001
|
||||
-900.951 450.001))
|
||||
(attach off)
|
||||
)
|
||||
(padstack Rect[A]Pad_1350.000000x1350.000000_um
|
||||
(shape (rect F.Cu -675 -675 675 675))
|
||||
(shape (rect B.Cu -675 -675 675 675))
|
||||
(attach off)
|
||||
)
|
||||
(padstack Rect[A]Pad_1800.000000x1800.000000_um
|
||||
(shape (rect F.Cu -900 -900 900 900))
|
||||
(shape (rect B.Cu -900 -900 900 900))
|
||||
(attach off)
|
||||
)
|
||||
(padstack "Via[0-1]_600:300_um"
|
||||
(shape (circle F.Cu 600))
|
||||
(shape (circle B.Cu 600))
|
||||
(attach off)
|
||||
)
|
||||
)
|
||||
(network
|
||||
(net GND
|
||||
(pins C3-2 C2-1 Y1-2 Y1-3 J2-6 R1-2 C4-2 U1-3 U1-5 U1-21 C1-1)
|
||||
)
|
||||
(net "Net-(U1-XTAL2{slash}PB7)"
|
||||
(pins Y1-4 U1-8 C1-2)
|
||||
)
|
||||
(net "Net-(U1-XTAL1{slash}PB6)"
|
||||
(pins C2-2 Y1-1 U1-7)
|
||||
)
|
||||
(net +5V
|
||||
(pins C3-1 J2-1 C4-1 U1-4 U1-6 U1-18 U1-20)
|
||||
)
|
||||
(net "Net-(D1-A)"
|
||||
(pins D1-2 U1-30)
|
||||
)
|
||||
(net "Net-(D1-K)"
|
||||
(pins D1-1 R1-1)
|
||||
)
|
||||
(net /MOSI
|
||||
(pins J2-3 U1-15)
|
||||
)
|
||||
(net /RESET
|
||||
(pins J2-2 U1-29)
|
||||
)
|
||||
(net /MISO
|
||||
(pins J2-4 U1-16)
|
||||
)
|
||||
(net /SCK
|
||||
(pins J2-5 U1-17)
|
||||
)
|
||||
(net /COL0
|
||||
(pins SW4-2 SW4-2@1 SW7-2 SW7-2@1 SW10-2 SW10-2@1 SW1-2 SW1-2@1 U1-12)
|
||||
)
|
||||
(net /ROW0
|
||||
(pins SW2-1 SW2-1@1 SW3-1 SW3-1@1 SW1-1 SW1-1@1 U1-23)
|
||||
)
|
||||
(net /COL1
|
||||
(pins SW2-2 SW2-2@1 SW5-2 SW5-2@1 SW8-2 SW8-2@1 U1-13 SW11-2 SW11-2@1)
|
||||
)
|
||||
(net /COL2
|
||||
(pins SW12-2 SW12-2@1 SW9-2 SW9-2@1 SW3-2 SW3-2@1 SW6-2 SW6-2@1 U1-14)
|
||||
)
|
||||
(net /ROW1
|
||||
(pins SW4-1 SW4-1@1 SW5-1 SW5-1@1 SW6-1 SW6-1@1 U1-24)
|
||||
)
|
||||
(net /ROW2
|
||||
(pins SW7-1 SW7-1@1 SW9-1 SW9-1@1 SW8-1 SW8-1@1 U1-25)
|
||||
)
|
||||
(net /ROW3
|
||||
(pins SW10-1 SW10-1@1 SW12-1 SW12-1@1 U1-26 SW11-1 SW11-1@1)
|
||||
)
|
||||
(net "unconnected-(U1-PD6-Pad10)"
|
||||
(pins U1-10)
|
||||
)
|
||||
(net "unconnected-(U1-ADC6-Pad19)"
|
||||
(pins U1-19)
|
||||
)
|
||||
(net "unconnected-(U1-PD3-Pad1)"
|
||||
(pins U1-1)
|
||||
)
|
||||
(net "unconnected-(U1-PD2-Pad32)"
|
||||
(pins U1-32)
|
||||
)
|
||||
(net "unconnected-(U1-PD1-Pad31)"
|
||||
(pins U1-31)
|
||||
)
|
||||
(net "unconnected-(U1-PD7-Pad11)"
|
||||
(pins U1-11)
|
||||
)
|
||||
(net "unconnected-(U1-PD4-Pad2)"
|
||||
(pins U1-2)
|
||||
)
|
||||
(net "unconnected-(U1-PC4-Pad27)"
|
||||
(pins U1-27)
|
||||
)
|
||||
(net "unconnected-(U1-PD5-Pad9)"
|
||||
(pins U1-9)
|
||||
)
|
||||
(net "unconnected-(U1-PC5-Pad28)"
|
||||
(pins U1-28)
|
||||
)
|
||||
(net "unconnected-(U1-ADC7-Pad22)"
|
||||
(pins U1-22)
|
||||
)
|
||||
(class kicad_default +5V /COL0 /COL1 /COL2 /MISO /MOSI /RESET /ROW0 /ROW1
|
||||
/ROW2 /ROW3 /SCK GND "Net-(D1-A)" "Net-(D1-K)" "Net-(U1-XTAL1{slash}PB6)"
|
||||
"Net-(U1-XTAL2{slash}PB7)" "unconnected-(U1-ADC6-Pad19)" "unconnected-(U1-ADC7-Pad22)"
|
||||
"unconnected-(U1-PC4-Pad27)" "unconnected-(U1-PC5-Pad28)" "unconnected-(U1-PD1-Pad31)"
|
||||
"unconnected-(U1-PD2-Pad32)" "unconnected-(U1-PD3-Pad1)" "unconnected-(U1-PD4-Pad2)"
|
||||
"unconnected-(U1-PD5-Pad9)" "unconnected-(U1-PD6-Pad10)" "unconnected-(U1-PD7-Pad11)"
|
||||
(circuit
|
||||
(use_via "Via[0-1]_600:300_um")
|
||||
)
|
||||
(rule
|
||||
(width 200)
|
||||
(clearance 200)
|
||||
)
|
||||
)
|
||||
)
|
||||
(wiring
|
||||
)
|
||||
)
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,130 @@
|
|||
{
|
||||
"board": {
|
||||
"active_layer": 0,
|
||||
"active_layer_preset": "",
|
||||
"auto_track_width": true,
|
||||
"hidden_netclasses": [],
|
||||
"hidden_nets": [],
|
||||
"high_contrast_mode": 0,
|
||||
"net_color_mode": 1,
|
||||
"opacity": {
|
||||
"images": 0.6,
|
||||
"pads": 1.0,
|
||||
"shapes": 1.0,
|
||||
"tracks": 1.0,
|
||||
"vias": 1.0,
|
||||
"zones": 0.6
|
||||
},
|
||||
"selection_filter": {
|
||||
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||
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|
||||
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
|
@ -0,0 +1,618 @@
|
|||
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|
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|
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|
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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||||
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|
||||
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|
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||||
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||||
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|
||||
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|
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|
||||
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|
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|
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|
||||
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|
||||
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|
||||
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|
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|
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"same_local_global_label": "warning",
|
||||
"similar_label_and_power": "warning",
|
||||
"similar_labels": "warning",
|
||||
"similar_power": "warning",
|
||||
"simulation_model_issue": "ignore",
|
||||
"single_global_label": "ignore",
|
||||
"unannotated": "error",
|
||||
"unconnected_wire_endpoint": "warning",
|
||||
"unit_value_mismatch": "error",
|
||||
"unresolved_variable": "error",
|
||||
"wire_dangling": "error"
|
||||
}
|
||||
},
|
||||
"libraries": {
|
||||
"pinned_footprint_libs": [],
|
||||
"pinned_symbol_libs": []
|
||||
},
|
||||
"meta": {
|
||||
"filename": "3x4_tactswitch_ir_remote.kicad_pro",
|
||||
"version": 3
|
||||
},
|
||||
"net_settings": {
|
||||
"classes": [
|
||||
{
|
||||
"bus_width": 12,
|
||||
"clearance": 0.2,
|
||||
"diff_pair_gap": 0.25,
|
||||
"diff_pair_via_gap": 0.25,
|
||||
"diff_pair_width": 0.2,
|
||||
"line_style": 0,
|
||||
"microvia_diameter": 0.3,
|
||||
"microvia_drill": 0.1,
|
||||
"name": "Default",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"priority": 2147483647,
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 0.2,
|
||||
"via_diameter": 0.6,
|
||||
"via_drill": 0.3,
|
||||
"wire_width": 6
|
||||
}
|
||||
],
|
||||
"meta": {
|
||||
"version": 4
|
||||
},
|
||||
"net_colors": null,
|
||||
"netclass_assignments": null,
|
||||
"netclass_patterns": []
|
||||
},
|
||||
"pcbnew": {
|
||||
"last_paths": {
|
||||
"gencad": "",
|
||||
"idf": "",
|
||||
"netlist": "",
|
||||
"plot": "",
|
||||
"pos_files": "",
|
||||
"specctra_dsn": "3x4_tactswitch_ir_remote.dsn",
|
||||
"step": "",
|
||||
"svg": "",
|
||||
"vrml": ""
|
||||
},
|
||||
"page_layout_descr_file": ""
|
||||
},
|
||||
"schematic": {
|
||||
"annotate_start_num": 0,
|
||||
"bom_export_filename": "${PROJECTNAME}.csv",
|
||||
"bom_fmt_presets": [],
|
||||
"bom_fmt_settings": {
|
||||
"field_delimiter": ",",
|
||||
"keep_line_breaks": false,
|
||||
"keep_tabs": false,
|
||||
"name": "CSV",
|
||||
"ref_delimiter": ",",
|
||||
"ref_range_delimiter": "",
|
||||
"string_delimiter": "\""
|
||||
},
|
||||
"bom_presets": [],
|
||||
"bom_settings": {
|
||||
"exclude_dnp": false,
|
||||
"fields_ordered": [
|
||||
{
|
||||
"group_by": false,
|
||||
"label": "Reference",
|
||||
"name": "Reference",
|
||||
"show": true
|
||||
},
|
||||
{
|
||||
"group_by": false,
|
||||
"label": "Qty",
|
||||
"name": "${QUANTITY}",
|
||||
"show": true
|
||||
},
|
||||
{
|
||||
"group_by": true,
|
||||
"label": "Value",
|
||||
"name": "Value",
|
||||
"show": true
|
||||
},
|
||||
{
|
||||
"group_by": true,
|
||||
"label": "DNP",
|
||||
"name": "${DNP}",
|
||||
"show": true
|
||||
},
|
||||
{
|
||||
"group_by": true,
|
||||
"label": "Exclude from BOM",
|
||||
"name": "${EXCLUDE_FROM_BOM}",
|
||||
"show": true
|
||||
},
|
||||
{
|
||||
"group_by": true,
|
||||
"label": "Exclude from Board",
|
||||
"name": "${EXCLUDE_FROM_BOARD}",
|
||||
"show": true
|
||||
},
|
||||
{
|
||||
"group_by": true,
|
||||
"label": "Footprint",
|
||||
"name": "Footprint",
|
||||
"show": true
|
||||
},
|
||||
{
|
||||
"group_by": false,
|
||||
"label": "Datasheet",
|
||||
"name": "Datasheet",
|
||||
"show": true
|
||||
}
|
||||
],
|
||||
"filter_string": "",
|
||||
"group_symbols": true,
|
||||
"include_excluded_from_bom": true,
|
||||
"name": "Default Editing",
|
||||
"sort_asc": true,
|
||||
"sort_field": "Reference"
|
||||
},
|
||||
"connection_grid_size": 50.0,
|
||||
"drawing": {
|
||||
"dashed_lines_dash_length_ratio": 12.0,
|
||||
"dashed_lines_gap_length_ratio": 3.0,
|
||||
"default_line_thickness": 6.0,
|
||||
"default_text_size": 50.0,
|
||||
"field_names": [],
|
||||
"intersheets_ref_own_page": false,
|
||||
"intersheets_ref_prefix": "",
|
||||
"intersheets_ref_short": false,
|
||||
"intersheets_ref_show": false,
|
||||
"intersheets_ref_suffix": "",
|
||||
"junction_size_choice": 3,
|
||||
"label_size_ratio": 0.375,
|
||||
"operating_point_overlay_i_precision": 3,
|
||||
"operating_point_overlay_i_range": "~A",
|
||||
"operating_point_overlay_v_precision": 3,
|
||||
"operating_point_overlay_v_range": "~V",
|
||||
"overbar_offset_ratio": 1.23,
|
||||
"pin_symbol_size": 25.0,
|
||||
"text_offset_ratio": 0.15
|
||||
},
|
||||
"legacy_lib_dir": "",
|
||||
"legacy_lib_list": [],
|
||||
"meta": {
|
||||
"version": 1
|
||||
},
|
||||
"net_format_name": "",
|
||||
"page_layout_descr_file": "",
|
||||
"plot_directory": "",
|
||||
"space_save_all_events": true,
|
||||
"spice_current_sheet_as_root": false,
|
||||
"spice_external_command": "spice \"%I\"",
|
||||
"spice_model_current_sheet_as_root": true,
|
||||
"spice_save_all_currents": false,
|
||||
"spice_save_all_dissipations": false,
|
||||
"spice_save_all_voltages": false,
|
||||
"subpart_first_id": 65,
|
||||
"subpart_id_separator": 0
|
||||
},
|
||||
"sheets": [
|
||||
[
|
||||
"62f229a9-6f61-4fe9-9136-10bbaf782921",
|
||||
"Root"
|
||||
]
|
||||
],
|
||||
"text_variables": {}
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,666 @@
|
|||
{
|
||||
"done": [
|
||||
{
|
||||
"MultilayerAutoroute": [
|
||||
[
|
||||
{
|
||||
"pin": "C1-1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "C1-2",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "C2-1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "C2-2",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "C3-1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "C3-2",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "C4-1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "C4-2",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "D1-1",
|
||||
"layer": "B.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "D1-1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "D1-2",
|
||||
"layer": "B.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "D1-2",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "J2-1",
|
||||
"layer": "B.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "J2-1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "J2-2",
|
||||
"layer": "B.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "J2-2",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "J2-3",
|
||||
"layer": "B.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "J2-3",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "J2-4",
|
||||
"layer": "B.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "J2-4",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "J2-5",
|
||||
"layer": "B.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "J2-5",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "J2-6",
|
||||
"layer": "B.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "J2-6",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "R1-1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "R1-2",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW1-1",
|
||||
"layer": "B.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW1-1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW1-1@1",
|
||||
"layer": "B.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW1-1@1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW1-2",
|
||||
"layer": "B.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW1-2",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW1-2@1",
|
||||
"layer": "B.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW1-2@1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW10-1",
|
||||
"layer": "B.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW10-1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW10-1@1",
|
||||
"layer": "B.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW10-1@1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW10-2",
|
||||
"layer": "B.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW10-2",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW10-2@1",
|
||||
"layer": "B.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW10-2@1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW11-1",
|
||||
"layer": "B.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW11-1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW11-1@1",
|
||||
"layer": "B.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW11-1@1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW11-2",
|
||||
"layer": "B.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW11-2",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW11-2@1",
|
||||
"layer": "B.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW11-2@1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW12-1",
|
||||
"layer": "B.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW12-1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW12-1@1",
|
||||
"layer": "B.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW12-1@1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW12-2",
|
||||
"layer": "B.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW12-2",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW12-2@1",
|
||||
"layer": "B.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW12-2@1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW2-1",
|
||||
"layer": "B.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW2-1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW2-1@1",
|
||||
"layer": "B.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW2-1@1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW2-2",
|
||||
"layer": "B.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW2-2",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW2-2@1",
|
||||
"layer": "B.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW2-2@1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW3-1",
|
||||
"layer": "B.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW3-1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW3-1@1",
|
||||
"layer": "B.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW3-1@1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW3-2",
|
||||
"layer": "B.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW3-2",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW3-2@1",
|
||||
"layer": "B.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW3-2@1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW4-1",
|
||||
"layer": "B.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW4-1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW4-1@1",
|
||||
"layer": "B.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW4-1@1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW4-2",
|
||||
"layer": "B.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW4-2",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW4-2@1",
|
||||
"layer": "B.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW4-2@1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW5-1",
|
||||
"layer": "B.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW5-1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW5-1@1",
|
||||
"layer": "B.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW5-1@1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW5-2",
|
||||
"layer": "B.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW5-2",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW5-2@1",
|
||||
"layer": "B.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW5-2@1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW6-1",
|
||||
"layer": "B.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW6-1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW6-1@1",
|
||||
"layer": "B.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW6-1@1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW6-2",
|
||||
"layer": "B.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW6-2",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW6-2@1",
|
||||
"layer": "B.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW6-2@1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW7-1",
|
||||
"layer": "B.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW7-1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW7-1@1",
|
||||
"layer": "B.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW7-1@1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW7-2",
|
||||
"layer": "B.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW7-2",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW7-2@1",
|
||||
"layer": "B.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW7-2@1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW8-1",
|
||||
"layer": "B.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW8-1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW8-1@1",
|
||||
"layer": "B.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW8-1@1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW8-2",
|
||||
"layer": "B.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW8-2",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW8-2@1",
|
||||
"layer": "B.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW8-2@1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW9-1",
|
||||
"layer": "B.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW9-1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW9-1@1",
|
||||
"layer": "B.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW9-1@1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW9-2",
|
||||
"layer": "B.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW9-2",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW9-2@1",
|
||||
"layer": "B.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "SW9-2@1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "U1-1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "U1-10",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "U1-11",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "U1-12",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "U1-13",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "U1-14",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "U1-15",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "U1-16",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "U1-17",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "U1-18",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "U1-19",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "U1-2",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "U1-20",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "U1-21",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "U1-22",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "U1-23",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "U1-24",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "U1-25",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "U1-26",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "U1-27",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "U1-28",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "U1-29",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "U1-3",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "U1-30",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "U1-31",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "U1-32",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "U1-4",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "U1-5",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "U1-6",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "U1-7",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "U1-8",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "U1-9",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "Y1-1",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "Y1-2",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "Y1-3",
|
||||
"layer": "F.Cu"
|
||||
},
|
||||
{
|
||||
"pin": "Y1-4",
|
||||
"layer": "F.Cu"
|
||||
}
|
||||
],
|
||||
{
|
||||
"anterouter": {
|
||||
"fanout_clearance": 200.0
|
||||
},
|
||||
"planar": {
|
||||
"principal_layer": 0,
|
||||
"presort_by": "RatlineIntersectionCountAndLength",
|
||||
"permutate": true,
|
||||
"router": {
|
||||
"routed_band_width": 100.0,
|
||||
"wrap_around_bands": true,
|
||||
"squeeze_through_under_bends": true
|
||||
},
|
||||
"timeout": {
|
||||
"initial": 1.0,
|
||||
"progress_bonus": 0.005
|
||||
}
|
||||
},
|
||||
"timeout": {
|
||||
"initial": 10.0,
|
||||
"progress_bonus": 0.15
|
||||
}
|
||||
}
|
||||
]
|
||||
}
|
||||
],
|
||||
"undone": []
|
||||
}
|
||||
Loading…
Reference in New Issue