mirror of https://gitlab.com/nakst/essence
112 lines
3.7 KiB
C
112 lines
3.7 KiB
C
#ifndef ARCH_X86_64_HEADER
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#define ARCH_X86_64_HEADER
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#define LOW_MEMORY_MAP_START (0xFFFFFE0000000000)
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#define LOW_MEMORY_LIMIT (0x100000) // The first 1MB is mapped here.
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// --------------------------------- Standardised IO ports.
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#define IO_PIC_1_COMMAND (0x0020)
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#define IO_PIC_1_DATA (0x0021)
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#define IO_PIT_DATA (0x0040)
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#define IO_PIT_COMMAND (0x0043)
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#define IO_PS2_DATA (0x0060)
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#define IO_PC_SPEAKER (0x0061)
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#define IO_PS2_STATUS (0x0064)
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#define IO_PS2_COMMAND (0x0064)
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#define IO_RTC_INDEX (0x0070)
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#define IO_RTC_DATA (0x0071)
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#define IO_PIC_2_COMMAND (0x00A0)
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#define IO_PIC_2_DATA (0x00A1)
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#define IO_BGA_INDEX (0x01CE)
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#define IO_BGA_DATA (0x01CF)
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#define IO_ATA_1 (0x0170) // To 0x0177.
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#define IO_ATA_2 (0x01F0) // To 0x01F7.
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#define IO_COM_4 (0x02E8) // To 0x02EF.
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#define IO_COM_2 (0x02F8) // To 0x02FF.
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#define IO_ATA_3 (0x0376)
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#define IO_VGA_AC_INDEX (0x03C0)
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#define IO_VGA_AC_WRITE (0x03C0)
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#define IO_VGA_AC_READ (0x03C1)
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#define IO_VGA_MISC_WRITE (0x03C2)
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#define IO_VGA_MISC_READ (0x03CC)
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#define IO_VGA_SEQ_INDEX (0x03C4)
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#define IO_VGA_SEQ_DATA (0x03C5)
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#define IO_VGA_DAC_READ_INDEX (0x03C7)
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#define IO_VGA_DAC_WRITE_INDEX (0x03C8)
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#define IO_VGA_DAC_DATA (0x03C9)
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#define IO_VGA_GC_INDEX (0x03CE)
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#define IO_VGA_GC_DATA (0x03CF)
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#define IO_VGA_CRTC_INDEX (0x03D4)
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#define IO_VGA_CRTC_DATA (0x03D5)
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#define IO_VGA_INSTAT_READ (0x03DA)
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#define IO_COM_3 (0x03E8) // To 0x03EF.
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#define IO_ATA_4 (0x03F6)
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#define IO_COM_1 (0x03F8) // To 0x03FF.
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#define IO_PCI_CONFIG (0x0CF8)
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#define IO_PCI_DATA (0x0CFC)
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// --------------------------------- Interrupt vectors.
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// Interrupt vectors:
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// 0x00 - 0x1F: CPU exceptions
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// 0x20 - 0x2F: PIC (disabled, spurious)
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// 0x30 - 0x4F: Timers and low-priority IPIs.
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// 0x50 - 0x6F: APIC (standard)
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// 0x70 - 0xAF: MSI
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// 0xF0 - 0xFE: High-priority IPIs
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// 0xFF: APIC (spurious interrupt)
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#define TIMER_INTERRUPT (0x40)
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#define YIELD_IPI (0x41)
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#define IRQ_BASE (0x50)
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#define CALL_FUNCTION_ON_ALL_PROCESSORS_IPI (0xF0)
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#define KERNEL_PANIC_IPI (0) // NMIs ignore the interrupt vector.
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#define INTERRUPT_VECTOR_MSI_START (0x70)
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#define INTERRUPT_VECTOR_MSI_COUNT (0x40)
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// --------------------------------- Forward declarations.
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extern "C" void gdt_data();
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extern "C" void processorGDTR();
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extern "C" uint64_t ProcessorReadCR3();
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extern "C" uintptr_t ProcessorGetRSP();
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extern "C" uintptr_t ProcessorGetRBP();
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extern "C" uint64_t ProcessorReadMXCSR();
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extern "C" void ProcessorInstallTSS(uint32_t *gdt, uint32_t *tss);
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extern "C" void ProcessorAPStartup();
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extern "C" void SSSE3Framebuffer32To24Copy(volatile uint8_t *destination, volatile uint8_t *source, size_t pixelGroups);
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extern "C" uintptr_t _KThreadTerminate;
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extern bool pagingNXESupport;
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extern bool pagingPCIDSupport;
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extern bool pagingSMEPSupport;
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extern bool pagingTCESupport;
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extern volatile uint64_t timeStampCounterSynchronizationValue;
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extern "C" bool simdSSE3Support;
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extern "C" bool simdSSSE3Support;
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extern uintptr_t bootloaderInformationOffset;
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struct NewProcessorStorage {
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struct CPULocalStorage *local;
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uint32_t *gdt;
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};
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NewProcessorStorage AllocateNewProcessorStorage(struct ACPIProcessor *archCPU);
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extern "C" void SetupProcessor2(struct NewProcessorStorage *);
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uintptr_t GetBootloaderInformationOffset();
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void ArchDelay1Ms(); // Spin for approximately 1ms. Use only during initialisation. Not thread-safe.
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uint64_t ArchGetTimeFromPITMs();
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void *ACPIGetRSDP();
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uint8_t ACPIGetCenturyRegisterIndex();
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size_t ProcessorSendIPI(uintptr_t interrupt, bool nmi = false, int processorID = -1); // Returns the number of processors the IPI was *not* sent to.
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void ArchSetPCIIRQLine(uint8_t slot, uint8_t pin, uint8_t line);
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#endif
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