mirror of https://gitlab.com/nakst/essence
592 lines
10 KiB
ArmAsm
592 lines
10 KiB
ArmAsm
; This file is part of the Essence operating system.
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; It is released under the terms of the MIT license -- see LICENSE.md.
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; Written by: nakst.
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[bits 32]
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[global ProcessorReset]
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[global ProcessorDebugOutputByte]
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[global ProcessorIn16]
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[global ProcessorIn32]
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[global ProcessorIn8]
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[global ProcessorOut16]
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[global ProcessorOut32]
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[global ProcessorOut8]
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[global ProcessorHalt]
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[global ProcessorDisableInterrupts]
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[global ProcessorEnableInterrupts]
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[global ProcessorAreInterruptsEnabled]
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[global ProcessorSetLocalStorage]
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[global ProcessorReadCR3]
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[global ProcessorInvalidatePage]
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[global ProcessorInvalidateAllPages]
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[global ProcessorReadTimeStamp]
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[global ProcessorSetThreadStorage]
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[global ProcessorFakeTimerInterrupt]
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[global ProcessorSetAddressSpace]
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[global ProcessorFlushCodeCache]
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[global ProcessorAPStartup]
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[global GetLocalStorage]
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[global GetCurrentThread]
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[global ArchSwitchContext]
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[global processorGDTR]
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[global gdt_data]
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[global timeStampCounterSynchronizationValue]
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[extern ArchNextTimer]
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[extern InterruptHandler]
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[extern KThreadTerminate]
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[extern KernelInitialise]
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[extern PostContextSwitch]
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[extern SetupProcessor2]
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[extern Syscall]
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[extern installationID]
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[extern PCSetupCOM1]
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[extern PCDisablePIC]
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[extern PCProcessMemoryMap]
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[extern bootloaderID]
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[extern bootloaderInformationOffset]
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[section .bss]
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%define boot_stack_size 10000
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boot_stack: resb boot_stack_size
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%define idt_size 2048
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idt_data: resb idt_size
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%define cpu_local_storage_size (256 * 4 * 4)
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cpu_local_storage: resb cpu_local_storage_size
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cpu_local_index: resb 4
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timeStampCounterSynchronizationValue: resb 8
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[section .data]
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processorGDTR:
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times 8 db 0
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idt:
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.limit: dw idt_size - 1
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.base: dd idt_data
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align 4
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gdt_data:
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.null_entry: dq 0
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.code_entry: dd 0xFFFF ; 0x0008
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db 0
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dw 0xCF9A
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db 0
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.data_entry: dd 0xFFFF ; 0x0010
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db 0
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dw 0xCF92
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db 0
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.user_code: dd 0xFFFF ; 0x001B
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db 0
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dw 0xCFFA
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db 0
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.user_data: dd 0xFFFF ; 0x0023
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db 0
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dw 0xCFF2
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db 0
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.tss: dd 0x68 ; 0x0028
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db 0
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dw 0xE9
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db 0
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dq 0
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.local: times 256 dq 0 ; 0x0038 - 0x0838
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.gdt: dw (gdt_data.gdt - gdt_data - 1)
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.gdt2: dd gdt_data
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[section .text]
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[global _start]
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_start:
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; Save the bootloader ID and information offset.
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mov [bootloaderID],esi
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mov [bootloaderInformationOffset],edi
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; The MBR bootloader does not know the address of the RSDP.
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cmp edi,0
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jne .standard_acpi
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mov [0x7FE8],edi
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.standard_acpi:
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; Install the boot stack.
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mov esp,boot_stack + boot_stack_size
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; Load the installation ID.
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mov eax,[edi + 0x7FF0]
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mov [installationID + 0],eax
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mov eax,[edi + 0x7FF4]
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mov [installationID + 4],eax
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mov eax,[edi + 0x7FF8]
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mov [installationID + 8],eax
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mov eax,[edi + 0x7FFC]
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mov [installationID + 12],eax
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; Load the new GDT, saving the location of the bootstrap GDT.
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lgdt [gdt_data.gdt]
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sgdt [processorGDTR]
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; Move the identity paging the bootloader used to LOW_MEMORY_MAP_START.
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; Then, map the local APIC to LOCAL_APIC_BASE.
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mov eax,[0xFFFFF000]
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mov [0xFFFFFEC0],eax
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xor eax,eax
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mov [0xFFFFF000],eax
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mov eax,0xFEE00103
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mov [0xFFC00000 + (0xEC3FF << 2)],eax
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mov eax,cr3
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mov cr3,eax
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; Install the interrupt handlers
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mov ebx,idt_data
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%macro INSTALL_INTERRUPT_HANDLER 1
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mov edx,InterruptHandler%1
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call InstallInterruptHandler
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add ebx,8
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%endmacro
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%assign i 0
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%rep 256
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INSTALL_INTERRUPT_HANDLER i
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%assign i i+1
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%endrep
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; Setup the remaining things and call KernelInitialise
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call SetupProcessor1 ; Need to get SSE up before calling into C code.
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call PCSetupCOM1
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call PCDisablePIC
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call PCProcessMemoryMap
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call KernelInitialise
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; Fall-through.
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ProcessorReady:
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; Set the timer and become this CPU's idle thread.
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push 1
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call ArchNextTimer
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; Fall-through.
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ProcessorIdle:
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sti
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hlt
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jmp ProcessorIdle
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SetupProcessor1:
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; x87 FPU.
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fninit
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fldcw [.cw]
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jmp .cwa
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.cw: dw 0x037A
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.cwa:
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; Enable MMX, SSE and SSE2.
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; TODO Check these are actually present!
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mov eax,cr0
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mov ebx,cr4
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and eax,~4
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or eax,2
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or ebx,512 + 1024
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mov cr0,eax
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mov cr4,ebx
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; Setup the local storage.
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; This creates a new data segment in the GDT pointing to a unique 16-byte block of cpu_local_storage,
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; and updates FS to use the data segment.
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mov eax,[cpu_local_index]
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mov ebx,eax
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shl ebx,4
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add ebx,cpu_local_storage
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mov edx,ebx
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shl ebx,16
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or ebx,0x0000FFFF
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mov ecx,edx
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shr ecx,16
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and edx,0xFF000000
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or edx,0x00CF9200
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or dl,cl
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mov dword [gdt_data.local + eax * 8 + 0],ebx
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mov dword [gdt_data.local + eax * 8 + 4],edx
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lea eax,[0x0038 + eax * 8]
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mov fs,ax
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inc dword [cpu_local_index]
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; Enable global pages.
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mov eax,cr4
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or eax,1 << 7
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mov cr4,eax
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; Enable write protect, so copy-on-write works in the kernel, and MMArchSafeCopy will page fault in read-only regions.
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mov eax,cr0
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or eax,1 << 16
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mov cr0,eax
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; Load the IDTR.
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lidt [idt]
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sti
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; Enable the APIC.
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; TODO Check it is actually present!
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mov ecx,0x1B
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rdmsr
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or eax,0x800
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wrmsr
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; Set the spurious interrupt vector to 0xFF
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mov eax,0xEC3FF0F0
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mov ebx,[eax]
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or ebx,0x1FF
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mov [eax],ebx
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; Use the flat processor addressing model
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mov eax,0xEC3FF0E0
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mov dword [eax],0xFFFFFFFF
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; Make sure that no external interrupts are masked
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xor eax,eax
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mov [0xEC3FF080],eax
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; TODO More feature detection and initialisation!
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ret
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InstallInterruptHandler:
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mov word [ebx + 0],dx
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mov word [ebx + 2],0x0008
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mov word [ebx + 4],0x8E00
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shr edx,16
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mov word [ebx + 6],dx
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ret
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%macro INTERRUPT_HANDLER 1
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InterruptHandler%1:
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push dword 0 ; A fake error code
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push dword %1 ; The interrupt number
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jmp ASMInterruptHandler
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%endmacro
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%macro INTERRUPT_HANDLER_EC 1
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InterruptHandler%1:
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; The CPU already pushed an error code
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push dword %1 ; The interrupt number
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jmp ASMInterruptHandler
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%endmacro
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INTERRUPT_HANDLER 0
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INTERRUPT_HANDLER 1
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INTERRUPT_HANDLER 2
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INTERRUPT_HANDLER 3
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INTERRUPT_HANDLER 4
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INTERRUPT_HANDLER 5
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INTERRUPT_HANDLER 6
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INTERRUPT_HANDLER 7
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INTERRUPT_HANDLER_EC 8
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INTERRUPT_HANDLER 9
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INTERRUPT_HANDLER_EC 10
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INTERRUPT_HANDLER_EC 11
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INTERRUPT_HANDLER_EC 12
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INTERRUPT_HANDLER_EC 13
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INTERRUPT_HANDLER_EC 14
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INTERRUPT_HANDLER 15
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INTERRUPT_HANDLER 16
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INTERRUPT_HANDLER_EC 17
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INTERRUPT_HANDLER 18
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INTERRUPT_HANDLER 19
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INTERRUPT_HANDLER 20
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INTERRUPT_HANDLER 21
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INTERRUPT_HANDLER 22
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INTERRUPT_HANDLER 23
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INTERRUPT_HANDLER 24
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INTERRUPT_HANDLER 25
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INTERRUPT_HANDLER 26
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INTERRUPT_HANDLER 27
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INTERRUPT_HANDLER 28
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INTERRUPT_HANDLER 29
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INTERRUPT_HANDLER 30
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INTERRUPT_HANDLER 31
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%assign i 32
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%rep 224
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INTERRUPT_HANDLER i
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%assign i i+1
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%endrep
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ASMInterruptHandler:
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cld
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test byte [esp + 12],3
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jnz .have_esp
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; When ring 0 is interrupted, ESP and SS aren't pushed.
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; We push them ourselves here; we'll fix the order later.
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push eax
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push esp
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mov eax,ss
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xchg [esp + 4],eax
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push 1
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jmp .fixed
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.have_esp:
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push 0
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.fixed:
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push eax
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push ebx
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push ecx
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push edx
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push esi
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push edi
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push ebp
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mov ebx,esp
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and esp,~0xF
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fxsave [esp - 512]
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mov esp,ebx
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sub esp,512 + 16
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mov eax,ds
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push eax
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mov eax,0x10
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mov ds,ax
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mov eax,cr2
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push eax
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mov edx,[0xEC3FF080]
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push edx
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mov edx,0xF0
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mov [0xEC3FF080],edx ; Mask all interrupts.
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sti ; ...so there's no need to have the interrupt flag clear.
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push esp
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call InterruptHandler
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add esp,4
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xor eax,eax
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.return:
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cli ; Must be done before restoring CR8.
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pop edx
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mov [0xEC3FF080],edx
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add esp,4
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pop ebx
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mov ds,bx
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add esp,512 + 16
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mov ebx,esp
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and ebx,~0xF
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fxrstor [ebx - 512]
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or al,al
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jz .old_thread
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fninit ; New thread - initialise FPU.
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.old_thread:
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pop ebp
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pop edi
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pop esi
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pop edx
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pop ecx
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pop ebx
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pop eax
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test byte [esp],1
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jz .need_esp
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; When returning to ring 0, ESP and SS aren't popped.
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; So we do it manually here.
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add esp,8
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.need_esp:
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add esp,12
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iret
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ArchSwitchContext:
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cli
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mov eax,[esp + 16]
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mov [fs:8],eax
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mov ebx,[esp + 12]
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mov [fs:4],ebx
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mov edi,[esp + 8]
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mov ecx,[edi]
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mov edx,cr3
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cmp edx,ecx
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je .cont
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mov cr3,ecx
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.cont:
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mov eax,[esp + 4]
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mov ecx,[esp + 20]
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mov esp,eax ; Put the stack just below the context.
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push ecx
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push eax
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call PostContextSwitch
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add esp,8
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jmp ASMInterruptHandler.return
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ProcessorDebugOutputByte:
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%ifdef COM_OUTPUT
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mov dx,0x3F8 + 5
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.WaitRead:
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in al,dx
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and al,0x20
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cmp al,0
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je .WaitRead
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mov dx,0x3F8 + 0
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mov eax,[esp + 4]
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out dx,al
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%endif
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ret
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ProcessorOut8:
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mov edx,[esp + 4]
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mov eax,[esp + 8]
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out dx,al
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ret
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ProcessorIn8:
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mov edx,[esp + 4]
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xor eax,eax
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in al,dx
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ret
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ProcessorOut16:
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mov edx,[esp + 4]
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mov eax,[esp + 8]
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out dx,ax
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ret
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ProcessorIn16:
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mov edx,[esp + 4]
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xor eax,eax
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in ax,dx
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ret
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ProcessorOut32:
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mov edx,[esp + 4]
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mov eax,[esp + 8]
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out dx,eax
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ret
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ProcessorIn32:
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mov edx,[esp + 4]
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xor eax,eax
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in eax,dx
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ret
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ProcessorReset:
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in al,0x64
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test al,2
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jne ProcessorReset
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mov al,0xFE
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out 0x64,al
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; Fall-through.
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ProcessorHalt:
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cli
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hlt
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jmp ProcessorHalt
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ProcessorDisableInterrupts:
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mov eax,0xE0 ; Still allow important IPIs to go through.
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mov [0xEC3FF080],eax
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ret
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ProcessorEnableInterrupts:
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xor eax,eax
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mov [0xEC3FF080],eax
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ret
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ProcessorAreInterruptsEnabled:
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xor al,al
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mov edx,[0xEC3FF080]
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or edx,edx
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jnz .done
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mov al,1
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.done:
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ret
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GetLocalStorage:
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mov eax,[fs:0]
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ret
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GetCurrentThread:
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mov eax,[fs:8]
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ret
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ProcessorSetLocalStorage:
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mov eax,[esp + 4]
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mov [fs:0],eax
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ret
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ProcessorReadCR3:
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mov eax,cr3
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ret
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ProcessorInvalidatePage:
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mov eax,[esp + 4]
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invlpg [eax]
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ret
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ProcessorInvalidateAllPages:
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; Toggle CR4.PGE to invalidate all TLB entries, including global entries.
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mov eax,cr4
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and eax,~(1 << 7)
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mov cr4,eax
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or eax,1 << 7
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mov cr4,eax
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ret
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ProcessorReadTimeStamp:
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rdtsc
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ret
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ProcessorSetThreadStorage:
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; TODO.
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ret
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ProcessorFakeTimerInterrupt:
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int 0x40
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ret
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ProcessorSetAddressSpace:
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mov eax,[esp + 4]
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mov edx,[eax]
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mov eax,cr3
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cmp eax,edx
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je .cont
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mov cr3,edx
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.cont:
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ret
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ProcessorFlushCodeCache:
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wbinvd
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ret
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SynchronizeTimeStampCounter:
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; TODO
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ret
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[bits 16]
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ProcessorAPStartup: ; This function must be less than 4KB in length (see drivers/acpi.cpp)
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mov ax,0x1000
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mov ds,ax
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mov byte [0xFC0],1 ; Indicate we've started.
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mov eax,[0xFF0]
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mov cr3,eax
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lgdt [0x1000 + gdt_data.gdt - gdt_data]
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mov eax,cr0
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or eax,1
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mov cr0,eax
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jmp 0x8:dword (.pmode - ProcessorAPStartup + 0x10000)
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[bits 32]
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.pmode:
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mov eax,0x10
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mov ds,ax
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mov es,ax
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mov ss,ax
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lgdt [gdt_data.gdt]
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mov esp,[0x10FD0]
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call SetupProcessor1
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call SynchronizeTimeStampCounter
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mov edi,[0x10FB0]
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push edi
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call SetupProcessor2
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mov byte [0x10FC0],2 ; Indicate the BSP can start the next processor.
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jmp ProcessorReady
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