mirror of https://gitlab.com/nakst/essence
when booting from EFI, accept any peripheral IRQ for PCI
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nakst
parent
cf0e16bc1c
commit
02e039b3f5
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@ -242,7 +242,7 @@ bool KPCIDevice::EnableSingleInterrupt(KIRQHandler irqHandler, void *context, co
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EnableFeatures(K_PCI_FEATURE_INTERRUPTS);
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if (KRegisterIRQ(interruptLine, irqHandler, context, cOwnerName)) {
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if (KRegisterIRQ(KBootedFromEFI() ? -1 : interruptLine, irqHandler, context, cOwnerName, this)) {
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return true;
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}
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@ -87,7 +87,8 @@ void EsPrint(const char *format, ...);
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typedef bool (*KIRQHandler)(uintptr_t interruptIndex /* tag for MSI */, void *context);
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// Interrupts are active high and level triggered, unless overridden by the ACPI MADT table.
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bool KRegisterIRQ(uintptr_t interruptIndex, KIRQHandler handler, void *context, const char *cOwnerName);
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bool KRegisterIRQ(intptr_t interruptIndex, KIRQHandler handler, void *context, const char *cOwnerName,
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struct KPCIDevice *pciDevice = nullptr /* do not use; see KPCIDevice::EnableSingleInterrupt */);
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struct KMSIInformation {
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// Both fields are zeroed if the MSI could not be registered.
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@ -13,7 +13,7 @@ typedef struct ACPIProcessor ArchCPU;
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#define TIMER_INTERRUPT (0x40)
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#define YIELD_IPI (0x41)
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// Note: IRQ_BASE is currently 0x50.
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#define IRQ_BASE (0x50)
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#define CALL_FUNCTION_ON_ALL_PROCESSORS_IPI (0xF0)
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#define KERNEL_PANIC_IPI (0) // NMIs ignore the interrupt vector.
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@ -78,6 +78,22 @@ uint8_t coreL1Commit[(0xFFFF800200000000 - 0xFFFF800100000000) >> (/* ENTRIES_PE
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#ifdef IMPLEMENTATION
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struct MSIHandler {
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KIRQHandler callback;
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void *context;
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};
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struct IRQHandler {
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KIRQHandler callback;
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void *context;
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intptr_t line;
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KPCIDevice *pciDevice;
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const char *cOwnerName;
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};
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MSIHandler msiHandlers[INTERRUPT_VECTOR_MSI_COUNT];
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IRQHandler irqHandlers[0x40];
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extern uintptr_t bootloaderInformationOffset;
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extern "C" bool simdSSE3Support;
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extern "C" bool simdSSSE3Support;
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@ -601,12 +617,78 @@ void ArchDelay1Ms() {
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}
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}
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struct MSIHandler {
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KIRQHandler callback;
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void *context;
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};
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bool SetupInterruptRedirectionEntry(uintptr_t _line) {
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KSpinlockAssertLocked(&scheduler.lock);
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MSIHandler msiHandlers[INTERRUPT_VECTOR_MSI_COUNT];
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static uint32_t alreadySetup = 0;
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if (alreadySetup & (1 << _line)) {
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return true;
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}
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// Work out which interrupt the IoApic will sent to the processor.
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// TODO Use the upper 4 bits for IRQ priority.
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uintptr_t line = _line;
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uintptr_t thisProcessorIRQ = line + IRQ_BASE;
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bool activeLow = false;
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bool levelTriggered = true;
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// If there was an interrupt override entry in the MADT table,
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// then we'll have to use that number instead.
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for (uintptr_t i = 0; i < acpi.interruptOverrideCount; i++) {
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ACPIInterruptOverride *interruptOverride = acpi.interruptOverrides + i;
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if (interruptOverride->sourceIRQ == line) {
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line = interruptOverride->gsiNumber;
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activeLow = interruptOverride->activeLow;
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levelTriggered = interruptOverride->levelTriggered;
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break;
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}
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}
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KernelLog(LOG_INFO, "Arch", "IRQ flags", "SetupInterruptRedirectionEntry - IRQ %d is active %z, %z triggered.\n",
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line, activeLow ? "low" : "high", levelTriggered ? "level" : "edge");
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ACPIIoApic *ioApic;
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bool foundIoApic = false;
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// Look for the IoApic to which this interrupt is sent.
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for (uintptr_t i = 0; i < acpi.ioapicCount; i++) {
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ioApic = acpi.ioApics + i;
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if (line >= ioApic->gsiBase && line < (ioApic->gsiBase + (0xFF & (ioApic->ReadRegister(1) >> 16)))) {
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foundIoApic = true;
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line -= ioApic->gsiBase;
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break;
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}
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}
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// We couldn't find the IoApic that handles this interrupt.
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if (!foundIoApic) {
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KernelLog(LOG_ERROR, "Arch", "no IOAPIC", "SetupInterruptRedirectionEntry - Could not find an IOAPIC handling interrupt line %d.\n", line);
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return false;
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}
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// A normal priority interrupt.
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uintptr_t redirectionTableIndex = line * 2 + 0x10;
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uint32_t redirectionEntry = thisProcessorIRQ;
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if (activeLow) redirectionEntry |= (1 << 13);
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if (levelTriggered) redirectionEntry |= (1 << 15);
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// Send the interrupt to the processor that registered the interrupt.
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ioApic->WriteRegister(redirectionTableIndex, 1 << 16); // Mask the interrupt while we modify the entry.
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ioApic->WriteRegister(redirectionTableIndex + 1, GetLocalStorage()->archCPU->apicID << 24);
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ioApic->WriteRegister(redirectionTableIndex, redirectionEntry);
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alreadySetup |= 1 << _line;
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return true;
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}
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void KUnregisterMSI(uintptr_t tag) {
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KSpinlockAcquire(&scheduler.lock);
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@ -638,88 +720,48 @@ KMSIInformation KRegisterMSI(KIRQHandler handler, void *context, const char *cOw
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return {};
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}
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#define IRQ_BASE 0x50
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KIRQHandler irqHandlers[0x20][0x10];
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void *irqHandlerContext[0x20][0x10];
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size_t usedIrqHandlers[0x20];
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bool KRegisterIRQ(uintptr_t interrupt, KIRQHandler handler, void *context, const char *cOwnerName) {
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bool KRegisterIRQ(intptr_t line, KIRQHandler handler, void *context, const char *cOwnerName, KPCIDevice *pciDevice) {
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KSpinlockAcquire(&scheduler.lock);
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EsDefer(KSpinlockRelease(&scheduler.lock));
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// Work out which interrupt the IoApic will sent to the processor.
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// TODO Use the upper 4 bits for IRQ priority.
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uintptr_t thisProcessorIRQ = interrupt + IRQ_BASE;
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// Register the IRQ handler.
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if (interrupt > 0x20) KernelPanic("KRegisterIRQ - Unexpected IRQ %d\n", interrupt);
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if (usedIrqHandlers[interrupt] == 0x10) {
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// There are too many overloaded interrupts.
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return false;
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}
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irqHandlers[interrupt][usedIrqHandlers[interrupt]] = handler;
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irqHandlerContext[interrupt][usedIrqHandlers[interrupt]] = context;
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KernelLog(LOG_INFO, "Arch", "register IRQ", "KRegisterIRQ - Registering IRQ %d to '%z'.\n",
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interrupt, cOwnerName);
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if (usedIrqHandlers[interrupt]) {
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// IRQ already registered.
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usedIrqHandlers[interrupt]++;
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return true;
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if (line == -1 && !pciDevice) {
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KernelPanic("KRegisterIRQ - Interrupt line is %d, and pciDevice is %x.\n", line, pciDevice);
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}
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usedIrqHandlers[interrupt]++;
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// Save the handler callback and context.
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bool activeLow = false;
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bool levelTriggered = true;
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if (line > 0x20 || line < -1) KernelPanic("KRegisterIRQ - Unexpected IRQ %d\n", line);
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bool found = false;
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// If there was an interrupt override entry in the MADT table,
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// then we'll have to use that number instead.
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for (uintptr_t i = 0; i < acpi.interruptOverrideCount; i++) {
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ACPIInterruptOverride *interruptOverride = acpi.interruptOverrides + i;
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if (interruptOverride->sourceIRQ == interrupt) {
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interrupt = interruptOverride->gsiNumber;
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activeLow = interruptOverride->activeLow;
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levelTriggered = interruptOverride->levelTriggered;
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for (uintptr_t i = 0; i < sizeof(irqHandlers) / sizeof(irqHandlers[0]); i++) {
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if (!irqHandlers[i].callback) {
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found = true;
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irqHandlers[i].callback = handler;
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irqHandlers[i].context = context;
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irqHandlers[i].line = line;
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irqHandlers[i].pciDevice = pciDevice;
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irqHandlers[i].cOwnerName = cOwnerName;
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break;
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}
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}
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KernelLog(LOG_INFO, "Arch", "IRQ flags", "KRegisterIRQ - IRQ %d is active %z, %z triggered.\n",
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interrupt, activeLow ? "low" : "high", levelTriggered ? "level" : "edge");
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ACPIIoApic *ioApic;
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bool foundIoApic = false;
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// Look for the IoApic to which this interrupt is sent.
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for (uintptr_t i = 0; i < acpi.ioapicCount; i++) {
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ioApic = acpi.ioApics + i;
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if (interrupt >= ioApic->gsiBase
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&& interrupt < (ioApic->gsiBase + (0xFF & (ioApic->ReadRegister(1) >> 16)))) {
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foundIoApic = true;
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interrupt -= ioApic->gsiBase;
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break;
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}
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}
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// We couldn't find the IoApic that handles this interrupt.
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if (!foundIoApic) {
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if (!found) {
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KernelLog(LOG_ERROR, "Arch", "too many IRQ handlers", "The limit of IRQ handlers was reached (%d), and the handler for '%z' was not registered.\n",
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sizeof(irqHandlers) / sizeof(irqHandlers[0]), cOwnerName);
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return false;
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}
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// A normal priority interrupt.
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uintptr_t redirectionTableIndex = interrupt * 2 + 0x10;
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uint32_t redirectionEntry = thisProcessorIRQ;
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if (activeLow) redirectionEntry |= (1 << 13);
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if (levelTriggered) redirectionEntry |= (1 << 15);
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KernelLog(LOG_INFO, "Arch", "register IRQ", "KRegisterIRQ - Registered IRQ %d to '%z'.\n", line, cOwnerName);
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// Mask the interrupt while we modify the entry.
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ioApic->WriteRegister(redirectionTableIndex, 1 << 16);
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// Send the interrupt to the processor that registered the interrupt.
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ioApic->WriteRegister(redirectionTableIndex + 1, GetLocalStorage()->archCPU->apicID << 24);
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ioApic->WriteRegister(redirectionTableIndex, redirectionEntry);
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if (line != -1) {
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if (!SetupInterruptRedirectionEntry(line)) {
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return false;
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}
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} else {
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SetupInterruptRedirectionEntry(9);
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SetupInterruptRedirectionEntry(10);
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SetupInterruptRedirectionEntry(11);
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}
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return true;
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}
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@ -1036,16 +1078,15 @@ extern "C" void InterruptHandler(InterruptContext *context) {
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acpi.lapic.EndOfInterrupt();
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} else if (interrupt >= INTERRUPT_VECTOR_MSI_START && interrupt < INTERRUPT_VECTOR_MSI_START + INTERRUPT_VECTOR_MSI_COUNT && local) {
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MSIHandler handler = msiHandlers[interrupt - INTERRUPT_VECTOR_MSI_START];
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MSIHandler *handler = &msiHandlers[interrupt - INTERRUPT_VECTOR_MSI_START];
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local->irqSwitchThread = false;
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if (!handler.callback) {
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if (!handler->callback) {
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KernelLog(LOG_ERROR, "Arch", "unexpected MSI", "Unexpected MSI vector %X (no handler).\n", interrupt);
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} else {
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handler.callback(interrupt - INTERRUPT_VECTOR_MSI_START, handler.context);
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handler->callback(interrupt - INTERRUPT_VECTOR_MSI_START, handler->context);
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}
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acpi.lapic.EndOfInterrupt();
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if (local->irqSwitchThread && scheduler.started && local->schedulerReady) {
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@ -1065,29 +1106,18 @@ extern "C" void InterruptHandler(InterruptContext *context) {
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} else if (interrupt >= IRQ_BASE && interrupt < IRQ_BASE + 0x20) {
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GetLocalStorage()->inIRQ = true;
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size_t overloads = usedIrqHandlers[interrupt - IRQ_BASE];
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bool handledInterrupt = false;
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uintptr_t line = interrupt - IRQ_BASE;
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KernelLog(LOG_VERBOSE, "Arch", "IRQ start", "IRQ start %d.\n", line);
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KernelLog(LOG_VERBOSE, "Arch", "IRQ start", "IRQ start %d.\n", interrupt - IRQ_BASE);
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for (uintptr_t i = 0; i < overloads; i++) {
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KIRQHandler handler = irqHandlers[interrupt - IRQ_BASE][i];
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if (handler(interrupt - IRQ_BASE, irqHandlerContext[interrupt - IRQ_BASE][i])) {
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handledInterrupt = true;
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}
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for (uintptr_t i = 0; i < sizeof(irqHandlers) / sizeof(irqHandlers[0]); i++) {
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IRQHandler *handler = &irqHandlers[i];
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if (!handler->callback) continue;
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if (handler->line != -1 && (uintptr_t) handler->line != line) continue;
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if (handler->line == -1 && line != 9 && line != 10 && line != 11) continue;
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handler->callback(interrupt - IRQ_BASE, handler->context);
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}
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KernelLog(LOG_VERBOSE, "Arch", "IRQ end", "IRQ end %d.\n", interrupt - IRQ_BASE);
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bool rejectedByAll = !handledInterrupt;
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if (rejectedByAll) {
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// TODO Now what?
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// KernelLog(LOG_ERROR, "Arch", "unhandled IRQ",
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// "InterruptHandler - Unhandled IRQ %d, rejected by %d %z\n",
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// interrupt, overloads, (overloads != 1) ? "overloads" : "overload");
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}
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KernelLog(LOG_VERBOSE, "Arch", "IRQ end", "IRQ end %d.\n", line);
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GetLocalStorage()->inIRQ = false;
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}
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@ -18,16 +18,14 @@ extern "C" void processorGDTR();
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extern "C" void SetupProcessor2(struct NewProcessorStorage *);
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extern "C" void ProcessorInstallTSS(uint32_t *gdt, uint32_t *tss);
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bool HasSSSE3Support();
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uintptr_t GetBootloaderInformationOffset();
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void ArchDelay1Ms(); // Spin for approximately 1ms. Use only during initialisation. Not thread-safe.
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struct NewProcessorStorage {
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struct CPULocalStorage *local;
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uint32_t *gdt;
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};
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NewProcessorStorage AllocateNewProcessorStorage(struct ACPIProcessor *archCPU);
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bool HasSSSE3Support();
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uintptr_t GetBootloaderInformationOffset();
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void ArchDelay1Ms(); // Spin for approximately 1ms. Use only during initialisation. Not thread-safe.
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#endif
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